Zdeněk Kotásek

Publications

• 2023

  LOJDA, J.; PÁNEK, R.; SEKANINA, L.; KOTÁSEK, Z. Automated Design and Usage of the Fault-Tolerant Dynamic Partial Reconfiguration Controller for FPGAs. Microelectronics Reliability, 2023, vol. 2023, no. 144, p. 1-16. ISSN: 0026-2714. Detail

• 2021

  LOJDA, J.; PÁNEK, R.; KOTÁSEK, Z. Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs. In Proceedings - 2021 24th Euromicro Conference on Digital System Design, DSD 2021. Palermo: Institute of Electrical and Electronics Engineers, 2021. p. 549-552. ISBN: 978-1-6654-2703-6. Detail

  LOJDA, J.; PÁNEK, R.; KOTÁSEK, Z. Automatically-Designed Fault-Tolerant Systems: Failed Partitions Recovery. In 2021 IEEE East-West Design and Test Symposium, EWDTS 2021 - Proceedings. Batumi: Institute of Electrical and Electronics Engineers, 2021. p. 26-33. ISBN: 978-1-6654-4503-0. Detail

  LOJDA, J.; PÁNEK, R.; PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; KOTÁSEK, Z. Testing Embedded Software Through Fault Injection: Case Study on Smart Lock. In 2021 IEEE 22nd Latin American Test Symposium, LATS 2021. Punta del Este: Institute of Electrical and Electronics Engineers, 2021. p. 80-85. ISBN: 978-1-6654-2057-0. Detail

  LOJDA, J.; PODIVÍNSKÝ, J.; ČEKAN, O.; KOTÁSEK, Z. Accelerating Tests of Arithmetic Circuits Through On-FPGA Stimuli Generation and Their Reduction. In International Conference on Electrical, Computer, Communications and Mechatronics Engineering, ICECCME 2021. Mauritius: Institute of Electrical and Electronics Engineers, 2021. p. 1628-1633. ISBN: 978-1-6654-1262-9. Detail

  PÁNEK, R.; LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Reliability Analysis of the FPGA Control System with Reconfiguration Hardening. In Proceedings - 2021 24th Euromicro Conference on Digital System Design, DSD 2021. Palermo: Institute of Electrical and Electronics Engineers, 2021. p. 553-556. ISBN: 978-1-6654-2703-6. Detail

• 2020

  LOJDA, J.; PÁNEK, R.; PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; KOTÁSEK, Z. Analysis of Software-Implemented Fault Tolerance: Case Study on Smart Lock. In 2020 IEEE East-West Design and Test Symposium, EWDTS 2020 - Proceedings. Varna: Institute of Electrical and Electronics Engineers, 2020. p. 24-28. ISBN: 978-1-7281-9899-6. Detail

  LOJDA, J.; PÁNEK, R.; PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; KOTÁSEK, Z. Hardening of Smart Electronic Lock Software against Random and Deliberate Faults. In Proceedings - Euromicro Conference on Digital System Design, DSD 2020. Kranj: Institute of Electrical and Electronics Engineers, 2020. p. 680-683. ISBN: 978-1-7281-9535-3. Detail

  LOJDA, J.; PODIVÍNSKÝ, J.; ČEKAN, O.; PÁNEK, R.; KRČMA, M.; KOTÁSEK, Z. Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem. In Proceedings - 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2020. Novi Sad: Institute of Electrical and Electronics Engineers, 2020. p. 1-4. ISBN: 978-1-7281-9938-2. Detail

  PÁNEK, R.; LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study. In 2020 International Symposium on VLSI Design, Automation, and Test (VLSI-DAT) : proceedings of technical papers. Hsinchu: IEEE Computer Society, 2020. p. 121-124. ISBN: 978-1-7281-6083-2. Detail

  PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; BURGET, R.; HRUŠKA, T.; KOTÁSEK, Z. Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination. In 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS). San José: IEEE Circuits and Systems Society, 2020. p. 1-4. ISBN: 978-1-7281-3427-7. Detail

  PODIVÍNSKÝ, J.; LOJDA, J.; PÁNEK, R.; ČEKAN, O.; KRČMA, M.; KOTÁSEK, Z. Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks. In 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS). San José: IEEE Circuits and Systems Society, 2020. p. 1-4. ISBN: 978-1-7281-3427-7. Detail

• 2019

  ČEKAN, O.; PODIVÍNSKÝ, J.; LOJDA, J.; PÁNEK, R.; KRČMA, M.; KOTÁSEK, Z. Smart Electronic Locks and Their Reliability. Proceedings of the 7th Prague Embedded Systems Workshop. Roztoky u Prahy: Czech Technical University, 2019. p. 4-5. ISBN: 978-80-01-06607-2. Detail

  ČEKAN, O.; PODIVÍNSKÝ, J.; LOJDA, J.; PÁNEK, R.; KRČMA, M.; KOTÁSEK, Z. Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards. In Proceedings of the 2019 22nd Euromicro Conference on Digital System Design. Kalithea: Institute of Electrical and Electronics Engineers, 2019. p. 506-513. ISBN: 978-1-7281-2861-0. Detail

  KRČMA, M.; KOTÁSEK, Z.; LOJDA, J. Detecting hard synapses faults in artificial neural networks. In 20th IEEE Latin American Test Symposium (LATS 2019). Santiago de Chile: IEEE Computer Society, 2019. p. 1-6. ISBN: 978-1-7281-1756-0. Detail

  LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems. In 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019. p. 93-96. ISBN: 978-1-7281-1756-0. Detail

  PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; BURGET, R.; HRUŠKA, T.; KOTÁSEK, Z. Multidimensional Pareto Frontiers Intersection: Processor Optimization Case Study. Proceedings of the 7th Prague Embedded Systems Workshop. Roztoky u Prahy: Czech Technical University, 2019. p. 20-21. ISBN: 978-80-01-06607-2. Detail

  PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; BURGET, R.; HRUŠKA, T.; KOTÁSEK, Z. Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study. In Proceedings of the 2019 22nd Euromicro Conference on Digital System Design. Kalithea: Institute of Electrical and Electronics Engineers, 2019. p. 597-600. ISBN: 978-1-7281-2861-0. Detail

  PODIVÍNSKÝ, J.; LOJDA, J.; KOTÁSEK, Z. Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller. In 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019. p. 97-100. ISBN: 978-1-7281-1756-0. Detail

  SZURMAN, K.; KOTÁSEK, Z. Fault Recovery for Coarse-Grained TMR Soft-Core Processor Using Partial Reconfiguration and State Synchronization. Proceedings of the 7th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2019. p. 6-7. ISBN: 978-80-01-06607-2. Detail

  SZURMAN, K.; KOTÁSEK, Z. Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery. In 20th IEEE Latin American Test Symposium (LATS 2019). Santiago: IEEE Computer Society, 2019. p. 32-35. ISBN: 978-1-7281-1756-0. Detail

  SZURMAN, K.; KOTÁSEK, Z. Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor neo430. In 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2019). Cluj-Napoca: IEEE Computer Society, 2019. p. 136-140. ISBN: 978-1-7281-0073-9. Detail

• 2018

  ČEKAN, O.; KOTÁSEK, Z. Random Test Generation Through a Probabilistic Constrained Grammar. INFORMAL PROCEEDINGS 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Budapešť: 2018. p. 5-8. Detail

  ČEKAN, O.; PÁNEK, R.; KOTÁSEK, Z. Input and Output Generation for the Verification of ALU: a Use Case. In Proceedings of 2018 IEEE East-West Design and Test Symposium, EWDTS 2018. Kazan: IEEE Computer Society, 2018. p. 331-336. ISBN: 978-1-5386-5710-2. Detail

  ČEKAN, O.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Program Generation Through a Probabilistic Constrained Grammar. In Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018. Praha: IEEE Computer Society, 2018. p. 214-220. ISBN: 978-1-5386-7376-8. Detail

  LOJDA, J.; KOTÁSEK, Z. Automatizace návrhu spolehlivých systémů a její dílčí komponenty. Počítačové architektury & diagnostika 2018. Stachy: Západočeská univerzita v Plzni, 2018. s. 5-8. ISBN: 978-80-261-0814-6. Detail

  LOJDA, J.; KOTÁSEK, Z. Fault Tolerance in HLS for the Purposes of Reliable System Design Automation. Proceedings of the 6th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2018. p. 31-32. ISBN: 978-80-01-06456-6. Detail

  LOJDA, J.; PODIVÍNSKÝ, J.; ČEKAN, O.; PÁNEK, R.; KOTÁSEK, Z. FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant Systems Design Automation. In Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018. p. 244-251. ISBN: 978-1-5386-7376-8. Detail

  LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis. In Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018. p. 80-86. ISBN: 978-1-5386-5710-2. Detail

  LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z.; KRČMA, M. Majority Type and Redundancy Level Influences on Redundant Data Types Approach for HLS. In 2018 16th Biennial Baltic Electronics Conference (BEC). Tallinn: IEEE Computer Society, 2018. p. 1-4. ISBN: 978-1-5386-7312-6. Detail

  PÁNEK, R.; LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation. In Proceedings of IEEE East-West Design & Test Symposium. Kazaň: IEEE Computer Society, 2018. p. 129-134. ISBN: 978-1-5386-5710-2. Detail

  PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; BURGET, R.; HRUŠKA, T.; KOTÁSEK, Z. A Framework for Optimizing a Processor to Selected Application. In Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018. p. 564-574. ISBN: 978-1-5386-5710-2. Detail

  PODIVÍNSKÝ, J.; KOTÁSEK, Z. Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller. Proceedings of the 6th Prague Embedded Systems Workshop. Roztoky u Prahy: Czech Technical University, 2018. p. 33-34. ISBN: 978-80-01-06456-6. Detail

  PODIVÍNSKÝ, J.; LOJDA, J.; ČEKAN, O.; KOTÁSEK, Z. Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-based Experimental Robot Controller. In Proceedings of the 2018 21st Euromicro Conference on Digital System Design. Praha: IEEE Computer Society, 2018. p. 229-236. ISBN: 978-1-5386-7376-8. Detail

  PODIVÍNSKÝ, J.; LOJDA, J.; KOTÁSEK, Z. FPGA-based Robot Controller: An Experimental Evaluation of Fault Tolerance Properties. INFORMAL PROCEEDINGS 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Budapešť: 2018. p. 9-12. Detail

  PODIVÍNSKÝ, J.; LOJDA, J.; KOTÁSEK, Z. An Experimental Evaluation of Fault-Tolerant FPGA-based Robot Controller. In Proceedings of IEEE East-West Design & Test Symposium. Kazan: IEEE Computer Society, 2018. p. 63-69. ISBN: 978-1-5386-5710-2. Detail

• 2017

  ČEKAN, O.; KOTÁSEK, Z. Random Test Stimuli Generation Based on a Probabilistic Grammar. Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017. p. 43-44. ISBN: 978-80-01-06178-7. Detail

  ČEKAN, O.; KOTÁSEK, Z. A Probabilistic Context-Free Grammar Based Random Test Program Generation. In Proceedings of 20th Euromicro Conference on Digital System Design. Vídeň: Technical University Wien, 2017. p. 356-359. ISBN: 978-1-5386-2145-5. Detail

  KRČMA, M.; KOTÁSEK, Z. Approximation accuracy of different FPNN types. Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017. p. 81-82. ISBN: 978-80-01-06178-7. Detail

  KRČMA, M.; KOTÁSEK, Z.; LOJDA, J. Comparison of FPNNs Models Approximation Capabilities and FPGA Resources Utilization. In Proceedings of IEEE 13th International Conference on Intelligent Computer Communication and Processing. Cluj-Nappoca: IEEE Computer Society, 2017. p. 125-132. ISBN: 978-1-5386-3368-7. Detail

  KRČMA, M.; LOJDA, J.; KOTÁSEK, Z. Triple Modular Redundancy Used in Field Programmable Neural Networks. In Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017. p. 1-6. ISBN: 978-1-5386-3299-4. Detail

  LOJDA, J.; KOTÁSEK, Z. A Basic Approach to Fault Tolerance of Data Paths of HLS-synthesized Systems and its Evaluation. Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017. p. 79-80. ISBN: 978-80-01-06178-7. Detail

  LOJDA, J.; KOTÁSEK, Z. Automatizace návrhu systémů odolných proti poruchám pomocí vysokoúrovňové syntézy. Počítačové architektury & diagnostika 2017. Smolenice: Slovenská technická univerzita v Bratislavě, 2017. s. 59-62. ISBN: 978-80-972784-0-3. Detail

  LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Redundant Data Types and Operations in HLS and their Use for a Robot Controller Unit Fault Tolerance Evaluation. In Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017. p. 359-364. ISBN: 978-1-5386-3299-4. Detail

  LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z.; KRČMA, M. Data Types and Operations Modifications: a Practical Approach to Fault Tolerance in HLS. In Proceedings of IEEE East-West Design & Test Symposium. Novi Sad: IEEE Computer Society, 2017. p. 273-278. ISBN: 978-1-5386-3299-4. Detail

  PODIVÍNSKÝ, J.; ČEKAN, O.; LOJDA, J.; ZACHARIÁŠOVÁ, M.; KRČMA, M.; KOTÁSEK, Z. Functional Verification Based Platform for Evaluating Fault Tolerance Properties. Microprocessors and Microsystems, 2017, vol. 52, no. 5, p. 145-159. ISSN: 0141-9331. Detail

  PODIVÍNSKÝ, J.; KOTÁSEK, Z. The Use of Functional Verification for Monitoring Impact of Faults in SRAM-based FPGAs. Proceedings of the 5th Prague Embedded Systems Workshop. Roztoky u Prahy: Faculty of Information Technology, Czech Technical University, 2017. p. 81-82. ISBN: 978-80-01-06178-7. Detail

  PODIVÍNSKÝ, J.; LOJDA, J.; ČEKAN, O.; PÁNEK, R.; KOTÁSEK, Z. Reliability Analysis and Improvement of FPGA-based Robot Controller. In Proceedings of the 2017 20th Euromicro Conference on Digital System Design. Vídeň: IEEE Computer Society, 2017. p. 337-344. ISBN: 978-1-5386-2145-5. Detail

  SZURMAN, K.; KOTÁSEK, Z. State Synchronization of Faulty Soft Core Processors in Reconfigurable TMR Architecture. Počítačové architektúry & diagnostika 2017. Smolenice: Slovak University of Technology in Bratislava, 2017. p. 51-54. ISBN: 978-80-972784-0-3. Detail

• 2016

  ČEKAN, O.; KOTÁSEK, Z. Software-implemented Fault-Tolerant Program Generation. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy: 2016. p. 13-13. ISBN: 978-80-01-05984-5. Detail

  ČEKAN, O.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Random Stimuli Generation Based on a Stochastic Context-Free Grammar. In Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016. p. 295-296. ISBN: 978-1-5090-5602-6. Detail

  KOTÁSEK, Z.; PODIVÍNSKÝ, J. Verification of Robot Controller for Evaluating Impacts of Faults in Electro-mechanical Systems. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy: 2016. p. 0-0. Detail

  KRČMA, M.; KOTÁSEK, Z. Fault Tolerant Field Programmable Neural Networks. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy: 2016. p. 0-0. Detail

  KRČMA, M.; KOTÁSEK, Z.; LOJDA, J. Implementation of Fault Tolerant Techniques into FPNNs. In Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016. p. 297-298. ISBN: 978-1-5090-5602-6. Detail

  KRČMA, M.; KOTÁSEK, Z.; LOJDA, J.; KAŠTIL, J. Comparsion of FPNNs models approximation capabilities and resources utilization. Proceedings of the Work in progress Session held in connection with DSD 2016. Limassol: Johannes Kepler University Linz, 2016. p. 1-2. ISBN: 978-3-902457-46-2. Detail

  LOJDA, J.; KOTÁSEK, Z. A Systematic Approach to the Description of Fault-tolerant Systems. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy: 2016. p. 0-0. Detail

  LOJDA, J.; PODIVÍNSKÝ, J.; KRČMA, M.; KOTÁSEK, Z. HLS-based Fault Tolerance Approach for SRAM-based FPGAs. In Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016. p. 301-302. ISBN: 978-1-5090-5602-6. Detail

  PODIVÍNSKÝ, J.; ČEKAN, O.; LOJDA, J.; KOTÁSEK, Z. Functional Verification as a Tool for Monitoring Impact of Faults in SRAM-based FPGAs. In Proceedings of the 2016 International Conference on Field Programmable Technology. Xi'an: IEEE Computer Society, 2016. p. 293-294. ISBN: 978-1-5090-5602-6. Detail

  PODIVÍNSKÝ, J.; ČEKAN, O.; LOJDA, J.; KOTÁSEK, Z. Verification of Robot Controller for Evaluating Impacts of Faults in Electro-mechanical Systems. In Proceedings of the 19th Euromicro Conference on Digital Systems Design. Limassol: IEEE Computer Society, 2016. p. 487-494. ISBN: 978-1-5090-2816-0. Detail

  SZURMAN, K.; MIČULKA, L.; KOTÁSEK, Z. Towards a State Synchronization Methodology for Recovery Process after Partial Reconfiguration of Fault Tolerant Systems. Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy: 2016. p. 0-0. ISBN: 978-80-01-05984-5. Detail

  ZACHARIÁŠOVÁ, M.; KEKELYOVÁ, M.; KOTÁSEK, Z. Regression Test Suites Optimization for Application-specific Instruction-set Processors and Their Use for Dependability Analysis. In Proceedings of the 19th Euromicro Conference on Digital Systems Design. Limassol Cyprus: IEEE Computer Society, 2016. p. 380-387. ISBN: 978-1-5090-2816-0. Detail

• 2015

  ČEKAN, O.; PODIVÍNSKÝ, J.; KOTÁSEK, Z. Software Fault Tolerance: the Evaluation by Functional Verification. In Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015. p. 284-287. ISBN: 978-1-4673-8035-5. Detail

  ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Universal Pseudo-random Generation of Assembler Codes for Processors. Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Grenoble: COST, European Cooperation in Science and Technology, 2015. p. 70-73. Detail

  KEKELYOVÁ, M.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z.; HRUŠKA, T. Application of Evolutionary Algorithms for Optimization of Regression Suites. In IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015. p. 91-94. ISBN: 978-1-4799-6779-7. Detail

  KRČMA, M.; KAŠTIL, J.; KOTÁSEK, Z. Mapping trained neural networks to FPNNs. In IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015. p. 157-160. ISBN: 978-1-4799-6779-7. Detail

  KRČMA, M.; KOTÁSEK, Z.; KAŠTIL, J. Fault Tolerant Field Programmable Neural Networks. In 1st IEEE Nordic Circuits and Systems (NORCAS) Conference. Oslo: IEEE Computer Society, 2015. p. 1-4. ISBN: 978-1-4673-6575-8. Detail

  PODIVÍNSKÝ, J.; ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications. Microprocessors and Microsystems, 2015, vol. 39, no. 8, p. 1215-1230. ISSN: 0141-9331. Detail

  PODIVÍNSKÝ, J.; ZACHARIÁŠOVÁ, M.; ČEKAN, O.; KOTÁSEK, Z. FPGA Prototyping and Accelerated Verification of ASIPs. In IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Belgrade: IEEE Computer Society, 2015. p. 145-148. ISBN: 978-1-4799-6780-3. Detail

  PODIVÍNSKÝ, J.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Radiation Impact on Mechanical Application Driven by FPGA-based Controller. Proceedings of The Fourth Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Grenoble: COST, European Cooperation in Science and Technology, 2015. p. 13-16. Detail

  ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Automation and Optimization of Coverage-driven Verification. In Proceedings of the 18th Euromicro Conference on Digital Systems Design. Funchal: IEEE Computer Society, 2015. p. 87-94. ISBN: 978-1-4673-8035-5. Detail

• 2014

  ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Solving of Constraint Satisfaction Problem. Proceedings of the 20th Conference STUDENT EEICT 2014. Volume 3. Brno: Faculty of Information Technology BUT, 2014. p. 291-295. ISBN: 978-80-214-4924-4. Detail

  KOTÁSEK, Z.; MIČULKA, L. Generic Partial Dynamic Reconfiguration Controller for Transient and Permanent Fault Mitigation in Fault Tolerant Systems Implemented Into FPGA. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Warszawa: IEEE Computer Society, 2014. p. 171-174. ISBN: 978-0-7695-5074-9. Detail

  MATUŠOVÁ, L.; KAŠTIL, J.; KOTÁSEK, Z. Automatic Construction of On-line Checking Circuits Based on Finite Automata. In 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014. p. 326-332. ISBN: 978-0-7695-5074-9. Detail

  PODIVÍNSKÝ, J.; ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications. In 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014. p. 312-319. ISBN: 978-1-4799-5793-4. Detail

  PODIVÍNSKÝ, J.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z. Complex Control System for Testing Fault-Tolerance Methodologies. Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Dresden: COST, European Cooperation in Science and Technology, 2014. p. 24-27. ISBN: 978-2-11-129175-1. Detail

  SZURMAN, K.; MIČULKA, L.; KOTÁSEK, Z. State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System. In 17th Euromicro Conference on Digital Systems Design. Verona: IEEE Computer Society, 2014. p. 704-707. ISBN: 978-1-4799-5793-4. Detail

  SZURMAN, K.; MIČULKA, L.; KOTÁSEK, Z. Towards a State Synchronization Methodology for Recovery Process after Partial Reconfiguration of Fault Tolerant Systems. In 9th IEEE International Conference on Computer Engineering and Systems. Káhira: IEEE Computer Society, 2014. p. 231-236. ISBN: 978-1-4799-6594-6. Detail

• 2013

  MIČULKA, L.; KOTÁSEK, Z. Synchronization Technique for TMR System After Dynamic Reconfiguration on FPGA. The Second Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN 2013). Avignon: Politecnico di Milano, 2013. p. 53-56. ISBN: 978-2-11-129175-1. Detail

  MIČULKA, L.; STRAKA, M.; KOTÁSEK, Z. Methodology for Fault Tolerant System Design Based on FPGA Into Limited Redundant Area. 16th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Santander: IEEE Computer Society, 2013. p. 227-234. ISBN: 978-0-7695-5074-9. Detail

  STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z.; MIČULKA, L. Fault Tolerant System Design and SEU Injection based Testing. Microprocessors and Microsystems, 2013, vol. 2013, no. 37, p. 155-173. ISSN: 0141-9331. Detail

  ZACHARIÁŠOVÁ, M.; BOLCHINI, C.; KOTÁSEK, Z. Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability. IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Karlovy Vary: IEEE Computer Society, 2013. p. 275-278. ISBN: 978-1-4673-6133-0. Detail

  ZACHARIÁŠOVÁ, M.; BOLCHINI, C.; KOTÁSEK, Z. Analysis and Comparison of Functional Verification and ATPG for Testing Design Reliability. Proceedings of The Second Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale. Avignon: COST, European Cooperation in Science and Technology, 2013. p. 35-38. ISBN: 978-2-11-129175-1. Detail

  ZACHARIÁŠOVÁ, M.; PŘIKRYL, Z.; HRUŠKA, T.; KOTÁSEK, Z. Automated Functional Verification of Application Specific Instruction-set Processors. IFIP Advances in Information and Communication Technology, 2013, vol. 4, no. 403, p. 128-138. ISSN: 1868-4238. Detail

• 2012

  BARTOŠ, P.; KOTÁSEK, Z. Reduction of Test Vectors Number based on Parasitic Capacity Extraction of Scan Chain Wires. Proceedings of CSE 2012 International Scientific Conference on Computer Science and Engineering. Košice: Faculty of Electrical Engineering and Informatics, University of Technology Košice, 2012. p. 162-169. ISBN: 978-80-8143-049-7. Detail

  KAŠTIL, J.; STRAKA, M.; MIČULKA, L.; KOTÁSEK, Z. Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA. 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Cesme-Izmir: IEEE Computer Society, 2012. p. 250-257. ISBN: 978-0-7695-4798-5. Detail

  KOTÁSEK, Z.; ŠKARVADA, J. Low Power Testing. In Design and Test Technology foír Dependable Systems-on-Chip. Hershey: IGI Global, 2012. p. 395-412. ISBN: 978-1-60960-212-3. Detail

  MIČULKA, L.; KOTÁSEK, Z. Design Sychronization after Partial Dynamic Reconfiguration of Fault Tolerant System. 15th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. Cesme-Izmir: IEEE Computer Society, 2012. p. 20-21. ISBN: 978-3-902457-33-2. Detail

  STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. Methodology for Reliability Analysis of FPGA-based Fault Tolerant Systems. CSE'2012 International Scientific Conference on Computer Science and Engineering. Košice: The University of Technology Košice, 2012. p. 146-153. ISBN: 978-80-8143-049-7. Detail

  STRAKA, M.; MIČULKA, L.; KAŠTIL, J.; KOTÁSEK, Z. Test Platform for Fault Tolerant Systems Design Qualities Verification. 15th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Tallin: IEEE Computer Society, 2012. p. 336-341. ISBN: 978-1-4673-1185-4. Detail

• 2011

  BARTOŠ, P.; KOTÁSEK, Z.; DOHNAL, J. Decreasing Test Time by Scan Chain Reorganization. IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011. p. 371-374. ISBN: 978-1-4244-9753-9. Detail

  STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. SEU Simulation Framework for Xilinx FPGA: First Step Towards Testing Fault Tolerant Systems. 14th EUROMICRO Conference on Digital System Design. Oulu: IEEE Computer Society, 2011. p. 223-230. ISBN: 978-0-7695-4494-6. Detail

  STRAKA, M.; KAŠTIL, J.; NOVOTNÝ, J.; KOTÁSEK, Z. Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA. IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011. p. 397-398. ISBN: 978-1-4244-9753-9. Detail

• 2010

  KOTÁSEK, Z.; ŠKARVADA, J.; STRNADEL, J. Reduction of Power Dissipation Through Parallel Optimization of Test Vector and Scan Register Sequences. Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vienna: IEEE Computer Society, 2010. p. 364-369. ISBN: 978-1-4244-6610-8. Detail

  KOTÁSEK, Z.; ŠKARVADA, J.; STRNADEL, J. The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. Proceedings of 13th Euromicro Conference on Digital System Design Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society, 2010. p. 644-651. ISBN: 978-0-7695-4171-6. Detail

  ŠKARVADA, J.; KOTÁSEK, Z.; STRNADEL, J. Optimalizace aplikace testu číslicových systémů pro nízký příkon. Brno: Fakulta informačních technologií VUT v Brně, 2010. 142 s. ISBN: 978-80-214-4209-2. Detail

  ŠKARVADA, J.; KOTÁSEK, Z.; STRNADEL, J. The Use of Genetic Algorithm to Reduce Power Consumption during Test Application. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Lecture Notes in Computer Science, ISSN 0302-9743, Vol. 6274. Berlin: Springer Verlag, 2010. p. 181-192. ISBN: 978-3-642-15322-8. ISSN: 0302-9743. Detail

  STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration. 13th EUROMICRO Conference on Digital System Design, DSD'2010. Lille: IEEE Computer Society, 2010. p. 365-372. ISBN: 978-0-7695-4171-6. Detail

  STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. Generic Partial Dynamic Reconfiguration Controller for Fault Tolerant Designs Based on FPGA. NORCHIP 2010. Tampere: IEEE Computer Society, 2010. p. 1-4. ISBN: 978-1-4244-8971-8. Detail

  STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. Methodology for Design of Highly Dependable Systems in FPGA. International Scientific Conference on Computer Science and Engineering. Košice: The University of Technology Košice, 2010. p. 186-193. ISBN: 978-80-8086-164-3. Detail

  STRAKA, M.; KAŠTIL, J.; KOTÁSEK, Z. Modern Fault Tolerant Architectures Based on Partial Dynamic Reconfiguration in FPGAs. Proceedings of the 2010 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS 2010. Wien: IEEE Computer Society, 2010. p. 173-176. ISBN: 978-1-4244-6610-8. Detail

• 2009

  KOTÁSEK, Z.; STRAKA, M. The Design of On-line Checkers and Their Use in Verification and Testing. Acta Electrotechnica et Informatica, 2009, vol. 2009, no. 3, p. 8-15. ISSN: 1335-8243. Detail

  STRAKA, M.; KOTÁSEK, Z. High Availability Fault Tolerant Architectures Implemented into FPGAs. 12th EUROMICRO Conference on Digital System Design DSD 2009. Patras: IEEE Computer Society, 2009. p. 108-116. ISBN: 978-0-7695-3782-5. Detail

  STRAKA, M.; KOTÁSEK, Z. Reliability Models for Fault Tolerant Architectures Based on FPGA. 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Faculty of Informatics MU, 2009. p. 239-239. ISBN: 978-80-87342-04-6. Detail

• 2008

  PEČENKA, T.; SEKANINA, L.; KOTÁSEK, Z. Evolution of Synthetic RTL Benchmark Circuits with Predefined Testability. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2008, vol. 13, no. 3, p. 1-21. ISSN: 1084-4309. Detail

  SEKANINA, L.; STAREČEK, L.; KOTÁSEK, Z.; GAJDA, Z. Polymorphic Gates in Design and Test of Digital Circuits. International Journal of Unconventional Computing, 2008, vol. 4, no. 2, p. 125-142. ISSN: 1548-7199. Detail

  ŠKARVADA, J.; KOTÁSEK, Z.; HERRMAN, T. Power Conscious RTL Test Scheduling. 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masaryk University, 2008. p. 265-265. ISBN: 978-80-7355-082-0. Detail

  ŠKARVADA, J.; KOTÁSEK, Z.; HERRMAN, T. Power Conscious RTL Test Scheduling. Proceedings of 11th Euromicro Conference on Digital Systems Design Architectures, Methods and Tools. Los Alamitos: IEEE Computer Society, 2008. p. 721-728. ISBN: 978-0-7695-3277-6. Detail

  ŠKARVADA, J.; KOTÁSEK, Z.; HERRMAN, T. Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. Microprocessors and Microsystems, 2008, vol. 32, no. 5, p. 296-302. ISSN: 0141-9331. Detail

  STAREČEK, L.; SEKANINA, L.; KOTÁSEK, Z. Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: IEEE Computer Society, 2008. p. 255-258. ISBN: 978-1-4244-2276-0. Detail

  STRAKA, M.; KOTÁSEK, Z. Design of FPGA-Based Dependable Systems. 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masaryk University, 2008. p. 240-247. ISBN: 978-80-7355-082-0. Detail

  STRAKA, M.; KOTÁSEK, Z.; WINTER, J. Digital Systems Architectures Based on On-line Checkers. 11th EUROMICRO Conference on Digital System Design DSD 2008. Parma: IEEE Computer Society, 2008. p. 81-87. ISBN: 978-0-7695-3277-6. Detail

  STRAKA, M.; KOTÁSEK, Z.; WINTER, J. The Design of Hardware Checkers for Verification and Diagnostic Purposes. CSE'2008 International Scientific Conference on Computer Science and Engineering. High Tatras - Stará Lesná: The University of Technology Košice, 2008. p. 320-327. ISBN: 978-80-8086-092-9. Detail

  STRNADEL, J.; PEČENKA, T.; KOTÁSEK, Z. Measuring Design for Testability Tool Effectiveness by Means of FITTest_BENCH06 Benchmark Circuits. Computing and Informatics, 2008, vol. 27, no. 6, p. 913-930. ISSN: 1335-9150. Detail

• 2007

  KOTÁSEK, Z.; KUBEK, J. Finite State Machine Localisation Based on IP Softcores Analysis. In 6th Electronic Circuits and Systems Conference. Conference Proceedings. Bratislava: Slovak University of Technology in Bratislava, 2007. p. 137-142. ISBN: 978-80-227-2697-9. Detail

  ŠKARVADA, J.; HERRMAN, T.; KOTÁSEK, Z. Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. In 10th EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN Architectures, Methods and Tools (DSD 2007). Lübeck: IEEE Computer Society, 2007. p. 611-618. ISBN: 0-7695-2978-X. Detail

  STAREČEK, L.; SEKANINA, L.; GAJDA, Z.; KOTÁSEK, Z.; PROKOP, R.; MUSIL, V. On Properties and Utilization of Some Polymorphic Gates. In 6th Electronic Circuits and Systems Conference (ECS 2007). Bratislava: Faculty of Informatics and Information Technology STU, 2007. p. 77-81. ISBN: 978-80-227-2697-9. Detail

  STRAKA, M.; KOTÁSEK, Z. Checker for Communication Protocol between IP Cores Based on FPGA. In 3rd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Faculty of Informatics MU, 2007. p. 193-200. ISBN: 978-80-7355-077-6. Detail

  STRAKA, M.; TOBOLA, J.; KOTÁSEK, Z. Checker Design for On-line Testing of Xilinx FPGA Communication. In The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Rome: IEEE Computer Society, 2007. p. 152-160. ISBN: 0-7695-2885-6. Detail

  TOBOLA, J.; KOTÁSEK, Z.; KOŘENEK, J.; MARTÍNEK, T.; STRAKA, M. Online Protocol Testing for FPGA Based Fault Tolerant Systems. In 10th EUROMICRO Conference on Digital System Design DSD 2007. Lubeck, Germany: IEEE Computer Society, 2007. p. 676-679. ISBN: 0-7695-2978-X. Detail

• 2006

  ČERNÝ, S.; STRUŽKA, P.; KOŘENEK, J.; MARTÍNEK, T.; KOTÁSEK, Z. FPGA Components in Simulink. In Proceedings of XXVIIIth International Autumn Colloquium ASIS 2006. Ostrava: 2006. p. 158-163. ISBN: 80-86840-26-3. Detail

  KOTÁSEK, Z.; STRNADEL, J. SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System. In Proceedings of the 13th IEEE International Symposium and Workshop on the Engineering of Computer-Based Systems (ECBS). Los Alamitos, CA: IEEE Computer Society, 2006. p. 497-498. ISBN: 0-7695-2546-6. Detail

  PEČENKA, T.; KOTÁSEK, Z. I-path Scheduling Algorithm for RT Level Circuits. In MEMICS 2006 2nd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Mikulov: 2006. p. 174-181. ISBN: 80-214-3287-X. Detail

  PEČENKA, T.; KOTÁSEK, Z.; SEKANINA, L. FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Testability Properties. In Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006. p. 285-289. ISBN: 1424401844. Detail

  PEČENKA, T.; STRNADEL, J.; KOTÁSEK, Z.; SEKANINA, L. Testability Estimation Based on Controllability and Observability Parameters. In Proceedings of the 9th EUROMICRO Conference on Digital System Design (DSD'06). IEEE CS. Cavtat: IEEE Computer Society, 2006. p. 504-514. ISBN: 0-7695-2609-8. Detail

  SEKANINA, L.; STAREČEK, L.; GAJDA, Z.; KOTÁSEK, Z. Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage. In Proc. of the 1st NASA/ESA Conference on Adaptive Hardware and Systems. Piscataway: IEEE Computer Society, 2006. p. 186-193. ISBN: 0-7695-2614-4. Detail

  SEKANINA, L.; STAREČEK, L.; KOTÁSEK, Z. Novel Logic Circuits Controlled by Vdd. In Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006. p. 85-86. ISBN: 1424401844. Detail

  ŠKARVADA, J.; KOTÁSEK, Z. Systém pro podporu vzdělávání v oblasti plánování testu vestavěných systémů. In Pedagogický software 2006. České Budějovice: Scientifik Pedagogical Publishing, 2006. s. 319-321. ISBN: 80-85645-56-4. Detail

• 2005

  DRÁBEK, V.; KOTÁSEK, Z. Handbook of Testing Electronic Systems. In Handbook of Testing Electronic Systems. Praha: Czech Technical University Publishing House, 2005. p. 235-243. ISBN: 80-01-03318-X. Detail

  KOTÁSEK, Z., STRNADEL, J. Testing Tools for Training and Education. In Proceedings of 12th International Conference on Mixed Design of Integrated Circuits and Systems. Krakow: Department of Microelectronics and Computer Science, Technical University of Lodz, 2005. p. 671-676. ISBN: 83-919289-9-3. Detail

  KOTÁSEK, Z., STRNADEL, J., PEČENKA, T. Methodology of Selecting Scan-Based Testability Improving Technique. In Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005. p. 186-189. ISBN: 963-9364-48-7. Detail

  PEČENKA, T., KOTÁSEK, Z., SEKANINA, L., STRNADEL, J. Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. In Proc. of the 2005 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2005. p. 51-58. ISBN: 0-7695-2399-4. Detail

  STRNADEL, J., KOTÁSEK, Z. Educational Tool for the Demonstration of Dft Principles Based on Scan Methodologies. In Proceedings of 8th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2005. p. 420-427. ISBN: 0-7695-2433-8. Detail

• 2004

  KOTÁSEK, Z. Survey of Partial Scan Methodologies. In Research and Training Action for System on Chip Design, 5th FP Project. Bratislava: Slovak Academy of Science, 2004. p. 1 ( p.) Detail

  KOTÁSEK, Z., MIKA, D., STRNADEL, J. The Identification of Registers in RTL Structures. In Preliminary Proceedings of 1st International Symposium on Leveraging Applications of Formal Methods ISOLA 2004. Technical Report TR-2004-6. Nicosia: Department of Computer Science of University of Cyprus, 2004. p. 317-320. ISBN: 3-540-41613. Detail

  KOTÁSEK, Z., PEČENKA, T., STRNADEL, J., MIKA, D., SEKANINA, L. An Overview of Research Activities in Digital Circuit Diagnosis and Benchmarking. In Proceedings of the Sixth Internation Scientific Conference Electronic Computers nad Informatics 2004. Košice: The University of Technology Košice, 2004. p. 229-234. ISBN: 80-8073-150-0. Detail

  KOTÁSEK, Z.; TUPEC, P. New approach to the FPGA testing based on the Boundary Scan. Proceedings of 38th International Conference MOSIS'04. Ostrava: 2004. p. 120-123. ISBN: 80-85988-98-4. Detail

  PEČENKA, T., KOTÁSEK, Z., SEKANINA, L., STRNADEL, J. Evolutionary Design of Synthetic RTL Benchmark Circuits. In Informal Digest of Papers, IEEE European Test Workshop 2004. Montpellier: IEEE Computer Society, 2004. p. 107-108. ISBN: 000000000. Detail

  PEČENKA, T., KOTÁSEK, Z., STRNADEL, J. Improving Testability Parameters of Pipelined Circuits Through the Identification of Testable Cores. In Proc. of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Bratislava: Slovak Academy of Science, 2004. p. 99-104. ISBN: 80-969117-9-1. Detail

• 2003

  KOTÁSEK, Z.; MIKA, D.; STRNADEL, J. Proceeding of IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems. Proceeding of IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems. Poznaň: Publishing House of Poznan University of Technology, 2003. p. 233-238. ISBN: 83-7143-557-6. Detail

  KOTÁSEK, Z.; MIKA, D.; STRNADEL, J. Test scheduling for embedded systems. Proceedings EUROMICRO Symposium on Digital System Design - Architectures, Methods and Tools DSD 2003. Belek: IEEE Computer Society Press, 2003. p. 463-467. ISBN: 0-7695-2003-0. Detail

  KOTÁSEK, Z.; TUPEC, P.; URBIŠ, H. Testing PCBs Based on Boundary Scan. Proceedings of International Carpathian Control Conference. Košice: The University of Technology Košice, 2003. p. 119-122. ISBN: 80-7099-509-2. Detail

  KOTÁSEK, Z.; URBIŠ, H. USB-to-IDE Adapter Design and Implementation. 6th International Workshopn on Electronics, Control, Measurment and Signals. Liberec: Liberec University of Technology, 2003. p. 315-319. ISBN: 80-7083-708-X. Detail

  MIKA, D.; KOTÁSEK, Z. Proc. of IFAC Workshop on Programmable Devices and Systems Conference. Proc. of IFAC Workshop on Programmable Devices and Systems Conference. Ostrava: Faculty of Electrical Engineering and Computer Science, VSB-TU Ostrava, 2003. p. 447-452. ISBN: 0-08-044130-0. Detail

  MIKA, D.; KOTÁSEK, Z. The Test Controller Model Based on The Timed Automaton. Proceedings of 37th International Conference MOSIS´03 Modelling and Simulation of Systems. Ostrava: 2003. p. 107-114. ISBN: 80-85988-86-0. Detail

• 2002

  MIKA, D.; KOTÁSEK, Z.; STRNADEL, J. Test Controller Design Based on VHDL Source File Analysis. Proceedings of The Fifth International Scientific Conference Electronic Computers and Informatics 2002. VIENALA Press, Edition: 55. Letná 42, 040 01 TU Košice: The University of Technology Košice, 2002. p. 135-141. ISBN: 80-7099-879-2. Detail

  STRNADEL, J.; KOTÁSEK, Z. Normalized Testability Measures at RT Level: Utilization and Reasons for Creation. Proceedings of 36th International Conference MOSIS`02 Modeling and Simulation of Systems. Vol. I. Ostrava: 2002. p. 297-304. ISBN: 80-85988-71-2. Detail

  STRNADEL, J.; KOTÁSEK, Z. Optimising Solution of the Scan Problem at RT Level Based on a Genetic Algorithm. Proceedings of 5th IEEE Design and Diagnostics of Electronics Circuits and Systems Workshop. Brno: Brno University of Technology, 2002. p. 44-51. ISBN: 80-214-2094-4. Detail

  STRNADEL, J.; KOTÁSEK, Z. Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. Proceedings of Euromicro Symposium on Digital System Design Architectures, Methods and Tools DSD'2002. Los Alamitos: IEEE Computer Society Press, 2002. p. 166-173. ISBN: 0-7695-1790-0. Detail

  ZBOŘIL, F., KOTÁSEK, Z., MIKA, D., STRNADEL, J. The Identification of Feedback Loops in RTL Structures. In Proceedings of The fifth International Scientific Conference Electronic Computers and Informatics 2002. Edition 55. Košice: The University of Technology Košice, 2002. p. 142-147. ISBN: 80-7099-879-2. Detail

• 2001

  KOTÁSEK, Z., STRNADEL, J. Analytic Approach to RTL Testability Analysis. In Proceedings of 7th Conference Student FEI 2001. Brno: Brno University of Technology, 2001. p. 363 ( p.)ISBN: 80-214-1860-5. Detail

  KOTÁSEK, Z.; RŮŽIČKA, R.; STRNADEL, J. Formal and Analytical Approaches to the Testability Analysis - the Comparison. Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2001. Gyor: SZIF-UNIVERSITAS Ltd., Hungary, 2001. p. 123-128. ISBN: 963-7175-16-4. Detail

  KOTÁSEK, Z.; RŮŽIČKA, R.; STRNADEL, J.; ZBOŘIL, F. Two Level Testability System. Proceedings of the 35th Spring International Conference MOSIS'01. Ostrava: 2001. p. 433-440. ISBN: 80-85988-57-7. Detail

  KOTÁSEK, Z.; STRNADEL, J. RTL Testability Analysis Based on Genetic Algorithm Implementation. Proceedings of the IWCIT'01. Ostrava: Faculty of Electrical Engineering and Computer Science, VSB-TU Ostrava, 2001. p. 83-88. ISBN: 80-7078-907-7. Detail

  KOTÁSEK, Z.; STRNADEL, J. RTL Testability Analysis Based on Genetic Algorithm Implementation. Proceedings of the Tenth ICNACSA. Plovdiv: unspecified agency, 2001. p. 89-89. Detail

  KOTÁSEK, Z.; STRNADEL, J.; RŮŽIČKA, R.; HLAVIČKA, J. Interactive Tool for Behavioral Level Testability Analysis. Proceedings of the IEEE ETW 2001. Stockholm: 2001. p. 117-119. Detail

• 1998

  ZBOŘIL, F., KOTÁSEK, Z. Nonstandard Automatic Test Pattern Generation Based on Neural Network Theory. In Proceedings of the ECI'98. Herlany, SR: SAV, 1998. p. 75-80. ISBN: 80-88786-94-0. Detail