Publication Details

Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA

STRAKA, M.; KAŠTIL, J.; NOVOTNÝ, J.; KOTÁSEK, Z. Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA. IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011. Cottbus: IEEE Computer Society, 2011. p. 397-398. ISBN: 978-1-4244-9753-9.
Czech title
Odolná sběrnice pro multi-jadrove systémy implementované do FPGA
Type
conference paper
Language
English
Authors
Straka Martin, Ing., Ph.D.
Kaštil Jan, Ing., Ph.D.
Novotný Jaroslav, Ing.
Kotásek Zdeněk, doc. Ing., CSc.
Keywords

FPGA, fault tolerant, bus, multicore, reconfiguration, on-line checker, TMR

Abstract

In the paper, a technique for design of highly dependable communication structure in SRAM-based FPGA is presented. The architecture of the multicore system and the structure of fault tolerant bus with cache memories are demonstrated. The fault tolerant properties are achieved by the replication and utilization of the self checking techniques together with partial dynamic reconfiguration. The experimental results show that presented system has small overhead if the high number of function units are used in the dependable system. All experiments were done on the Virtex5 and Virtex6 platform.

Published
2011
Pages
397–398
Proceedings
IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011
ISBN
978-1-4244-9753-9
Publisher
IEEE Computer Society
Place
Cottbus
BibTeX 
@inproceedings{BUT76277,
  author="Martin {Straka} and Jan {Kaštil} and Jaroslav {Novotný} and Zdeněk {Kotásek}",
  title="Advanced Fault Tolerant Bus for Multicore System Implemented in FPGA",
  booktitle="IEEE Design and Diagnostics of Electronic Circuits and Systems DDECS'2011",
  year="2011",
  pages="397--398",
  publisher="IEEE Computer Society",
  address="Cottbus",
  isbn="978-1-4244-9753-9"
}
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