Publication Details

Test Controller Design Based on VHDL Source File Analysis

MIKA, D.; KOTÁSEK, Z.; STRNADEL, J. Test Controller Design Based on VHDL Source File Analysis. Proceedings of The Fifth International Scientific Conference Electronic Computers and Informatics 2002. VIENALA Press, Edition: 55. Letná 42, 040 01 TU Košice: The University of Technology Košice, 2002. p. 135-141. ISBN: 80-7099-879-2.
Czech title
Návrh řadiče testu na základě VHDL analýzy
Type
conference paper
Language
English
Authors
Mika Daniel, Ing., Ph.D.
Kotásek Zdeněk, doc. Ing., CSc.
Strnadel Josef, Ing., Ph.D. (DCSY)
Keywords

Register Transfer Level, Data Transporter, Data Processor, The Unit Under Analysis

Abstract

In the paper the process of test controller design and synthesis on register transfer level (RTL) is described. The sequence of control, address and data signals together with circuit structure for which the test controller is designed are the input information of the problem. The methodology of transforming an RTL circuit into a labelled directed graph and then into VHDL source code will be presented. The ideas of test controller synthesis based on this information will be explicitly shown.

Published
2002
Pages
135–141
Proceedings
Proceedings of The Fifth International Scientific Conference Electronic Computers and Informatics 2002
Series
VIENALA Press, Edition: 55
ISBN
80-7099-879-2
Publisher
The University of Technology Košice
Place
Letná 42, 040 01 TU Košice
BibTeX 
@inproceedings{BUT10249,
  author="Daniel {Mika} and Zdeněk {Kotásek} and Josef {Strnadel}",
  title="Test Controller Design Based on VHDL Source File Analysis",
  booktitle="Proceedings of The Fifth International Scientific Conference Electronic Computers and Informatics 2002",
  year="2002",
  series="VIENALA Press, Edition: 55",
  pages="135--141",
  publisher="The University of Technology Košice",
  address="Letná 42, 040 01 TU Košice",
  isbn="80-7099-879-2"
}
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