Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor neo430

fault recovery, partial dynamic reconfiguration, state synchronization, soft-core processor, neo430, SEU, transient fault, SRAM FPGA

Reconfigurable fault tolerant (FT) architecture can be implemented into SRAM FPGA by using combination of Partial Dynamic Reconfiguration (PDR) and Triple Modular Redundancy (TMR). SRAM FPGAs are susceptible to Single Event Upsets (SEUs) which are the most common transient faults induced by cosmic radiation. SEU mitigation mechanism is required when SRAM FPGAs are integrated into safety-critical systems. An essential requirement for these systems is often to remain fail-operational and perform implemented functionality after the occurrence of a fault. In our research, we proposed a run-time FT architecture based on coarse-grained TMR with triplicated soft-core processor neo430, PDR for removing all transient SEU faults and the state synchronization allowing smooth state recovery from the inconsistent state when reconfiguration of failed processor instance was finished into the state where all three processors operate synchronously. This paper describes developed FT architecture and fault recovery strategy performing all necessary steps run-time and without additional blocking of the system functionality. The state synchronization for soft-core processor neo430 architecture is described in detail. Moreover, the paper presents developed PDR framework used for validation of proposed fault recovery strategy.