The Identification of Registers in RTL Structures

digital circuit diagnosis, test scheduling, resource selection, register resources, discrete mathematics, graph, relation, Hasse diagram, coverage problem, set minimization, register-transfer level

A highly efficient test schedule can be created for a given digital circuit if a proper test-scheduling algorithm is selected and if the circuit fulfils several criteria that affect the quality of a resulting test schedule significantly and independently on any scheduling algorithm. If a design for testability techniques are applied to the circuit structure, the way in which they are applied have a big impact on those circuit properties. Thus, it is feasible to deal with the relation between application of selected design for testability techniques and the quality of a resulting test schedule in detail. This is a wide research area. Our paper deals with the register selection technique through which a test will be applied. The paper presents a methodology for selecting registers for the test application in such a way that the cardinality of a set of selected registers is minimized and test resources allocated to functional units are shared in a maximum way. Proposed methodology is mathematically described, definitions are clearly illustrated and experimental results together with the future research perspectives are discussed.