Publication Details

Testing PCBs Based on Boundary Scan

KOTÁSEK, Z.; TUPEC, P.; URBIŠ, H. Testing PCBs Based on Boundary Scan. Proceedings of International Carpathian Control Conference. Košice: The University of Technology Košice, 2003. p. 119-122. ISBN: 80-7099-509-2.

Type

conference paper

Language

English

Authors

Kotásek Zdeněk, doc. Ing., CSc.
Tupec Pavel, Ing.
Urbiš Hynek, Ing.

Keywords

Boundary Scan, PCB, FPGA

Abstract

The paper describes a practical approach to testing PCBs with Xilinx FPGAs. The approach is based on a PCB netlist analysis, which is revealing the existing connections on the PCB through the Boundary Scan chain and comparing the two results. It is also supposed that the developed software tools will be used for debugging PCBs with Xilinx FPGAs. The goal of the research activities is to develop an easy to use an efficient and user- friendly software tools.

Published

2003

Pages

119–122

Proceedings

Proceedings of International Carpathian Control Conference

ISBN

80-7099-509-2

Publisher

The University of Technology Košice

Place

Košice

BibTeX

@inproceedings{BUT14165,
  author="Zdeněk {Kotásek} and Pavel {Tupec} and Hynek {Urbiš}",
  title="Testing PCBs Based on Boundary Scan",
  booktitle="Proceedings of International Carpathian Control Conference",
  year="2003",
  pages="119--122",
  publisher="The University of Technology Košice",
  address="Košice",
  isbn="80-7099-509-2"
}