Publication Details

Digital Systems Architectures Based on On-line Checkers

STRAKA, M.; KOTÁSEK, Z.; WINTER, J. Digital Systems Architectures Based on On-line Checkers. 11th EUROMICRO Conference on Digital System Design DSD 2008. Parma: IEEE Computer Society, 2008. p. 81-87. ISBN: 978-0-7695-3277-6.

Czech title

Type

conference paper

Language

English

Authors

Straka Martin, Ing., Ph.D.
Kotásek Zdeněk, doc. Ing., CSc.
Winter Jan, Ing.

Keywords

Fault Tolerant Systems, simple circuit, checker, FPGA, on-line testing, protocols

Abstract

In this paper, we present a methodology for generating VHDL descriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line checkers of communication protocols, counters, decoders, registers, comparators, etc. It is also demonstrated how a checker for more complex structures can be developed. We describe the possibilities of utilizing this approach in the design of Fault Tolerant Systems (FTS). Experimental results in terms of FPGA resources needed to synthesize different types of checkers are presented.

Published

2008

Pages

81–87

Proceedings

11th EUROMICRO Conference on Digital System Design DSD 2008

ISBN

978-0-7695-3277-6

Publisher

IEEE Computer Society

Place

Parma

BibTeX

@inproceedings{BUT27769,
  author="Martin {Straka} and Zdeněk {Kotásek} and Jan {Winter}",
  title="Digital Systems Architectures Based on On-line Checkers",
  booktitle="11th EUROMICRO Conference on Digital System Design DSD 2008",
  year="2008",
  pages="81--87",
  publisher="IEEE Computer Society",
  address="Parma",
  isbn="978-0-7695-3277-6",
  url="https://www.fit.vut.cz/research/publication/8621/"
}