Thesis Details
Implementace jednotky pro obsluhu bootování Intel FPGA
This thesis touches the topic of using FPGA technology in the field of computer networks, specifically for hardware acceleration of network traffic processing on a network card developed by the CESNET association. FPGA technology is popular mainly due to the possibility to easily reconfigure the chip and fix any errors or update the firmware. The thesis first discusses the design and implementation of a new unit for Intel FPGA, which will be able to communicate with the external configuration flash memory of the chip featured on the card mentioned above. It then goes on to address the design and implementation of a software tool that will allow, via the newly implemented firmware unit, to load new configuration data into the flash memory and force reconfiguration of the FPGA chip using this newly loaded data. Towards the end of the thesis, the functionality of the newly implemented system is tested in practice.
FPGA, configuration, Intel, Stratix 10, Agilex, Active Serial, QSPI, CESNET, bitstream, SDM, SDM Client, RSU, Mailbox
Hradiš Michal, Ing., Ph.D. (DCGM FIT BUT), člen
Jaroš Jiří, doc. Ing., Ph.D. (DCSY FIT BUT), člen
Křivka Zbyněk, Ing., Ph.D. (DIFS FIT BUT), člen
Lengál Ondřej, Ing., Ph.D. (DITS FIT BUT), člen
@bachelorsthesis{FITBT24669,
author = "Tom\'{a}\v{s} Hak",
type = "Bachelor's thesis",
title = "Implementace jednotky pro obsluhu bootov\'{a}n\'{i} Intel FPGA",
school = "Brno University of Technology, Faculty of Information Technology",
year = 2022,
location = "Brno, CZ",
language = "czech",
url = "https://www.fit.vut.cz/study/thesis/24669/"
}