Project Details
Formální přístup k plánování testu číslicových obvodů
Project Period: 1. 1. 2003 – 31. 12. 2005
Project Type: grant
Code: GP102/03/P176
Agency: Czech Science Foundation
Program: Postdoktorandské granty
computer science, informatics, computer diagnostics, digital circuits, testability
The topic of the proposed project is a methodology for scheduling of a test of digital circuits structure at Register Transfer (RT) level. The structure consist of mutually interconnected units. It is supposed that the circuit structure was previously analysed from the testability point of view and the method of the test application for each unit was proposed. For this purpose, the testability analysis methodology developed under main project and introduced by proposer in his doctoral thesis can be used. In the same thesis, a formal model of the circuit under analysis and its properties important from the diagnostic point of view were presented. A starting point is the model of the circuit and results of previously performed testability analysis which say how (along which paths and using which units) the test application process will run for each tested unit. The aim of this project is to develop a formal methodology which identifies optimal sequence of the test of units, synchronization of diagnostic data flows and possibility of parallelization. The optimality of solutions of these problems directly affects the test application time. Due to the formal approach to the problem and utilisation of formal models, problems of the test application and scheduling will be converted to problems of discrete mathematics and theoretical computer science and it will be possible to use algorithms offered by these disciplines to solve the problems. Along with previously solved testability analysis problem and with test generation tools, the complex solution of the diagnostics of comprehensive (embedded) systems will be provided to user.
2005
- RŮŽIČKA, R. On the Petri Net Based Test Scheduling. In Proceedings of the Work in Progress Session at Euromicro SEAA/DSD 2005. Linz: Johannes Kepler University Linz, 2005.
p. 18-19. ISBN: 3-902457-09-0. Detail
2004
- RŮŽIČKA, R., SEKANINA, L. A Platform for Demonstration of Analogue and Digital Circuits Evolution. In Proceedings of the Sixth Internation Scientific Conference Electronic Computers nad Informatics 2004. Košice: The University of Technology Košice, 2004.
p. 158-163. ISBN: 80-8073-150-0. Detail - RŮŽIČKA, R., ŠKARVADA, J. RTL Testability Verification System. In Proceedings of the Work In Progress Session of 30th Euromicro Conference. Linz: Johannes Kepler University Linz, 2004.
p. 101-102. ISBN: 3-902457-05-8. Detail - RŮŽIČKA, R., TUPEC, P. Formal Approach to Synthesis of a Test Controller. In Proceedings of Eleventh International Conference and Workshop on the Engineering of Computer-Based Systems. Los Alamitos, California: IEEE Computer Society, 2004.
p. 348-355. ISBN: 0-7695-2125-8. Detail
2003
- RŮŽIČKA, R. Testable Design Verification Using Petri Nets. Proceedings of Euromicro Symposium on Digital System Design 2003. Los Alamitos, CA: IEEE Computer Society Press, 2003.
p. 304-311. ISBN: 0-7695-2003-0. Detail - RŮŽIČKA, R.; ZBOŘIL, F. Representation of Datapath Structure in Predicate Logic and its Implementation in Prolog. Proceedings of International Carpathian Control Conference. Košice: The University of Technology Košice, 2003.
p. 727-730. ISBN: 80-7099-509-2. Detail - SEKANINA, L.; RŮŽIČKA, R. Easily Testable Image Operators: The Class of Circuits Where Evolution Beats Engineers. The 2003 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2003.
p. 135-144. ISBN: 0-7695-1977-6. Detail - SEKANINA, L.; RŮŽIČKA, R. On the Automatic Design of Testable Circuits. Proceedings of IEEE Workshop on Design nad Diagnostics of Electronic Circuits and Systems. Poznań: Publishing House of Poznan University of Technology, 2003.
p. 299-300. ISBN: 83-7143-557-6. Detail