Project Details

Moderní metody syntézy číslicových systémů

Project Period: 1. 1. 2004 – 31. 12. 2006

Project Type: grant

Code: GA102/04/0737

Agency: Czech Science Foundation

Program: Standardní projekty

English title
Modern Methods of Digital Systems Design
Type
grant
Keywords

digital system synthesis, digital system diagnostics

Abstract

The goal of the project is to develop, implement and verify methodologies based on approaches which are new, non-standard and not utilised in design systems yet. Our attention will be mainly paid to utilisation of biology inspired techniques and formal approaches and their merging.

The objectives of the project are formulated in the following way:

1. The identification of biology inspired techniques applicable for the synthesis of digital systems.

2. The development of biology inspired methodologies to be utilised in the following procedures during a  digital  synthesis: design and synthesis, testability analysis and synthesis for testability, adaptability of the system during its operation, providing fault tolerance during system operation.

3. The definition of utilising the principles of formal approaches during a digital system synthesis, the main attention will be paid especially to IP core based systems.

4. The development of formal approaches to be utilised in the following procedures during the design of digital systems: design and synthesis, testability analysis and synthesis for testability.

5. The development of methodologies based on merging both techniques enabling to create biology inspired techniques reflecting testability aspects.

6. The verification of the methodologies on benchmark circuits and practical designs.

Team members
Kotásek Zdeněk, doc. Ing., CSc. – research leader
Bryan Luděk, Ing., Ph.D.
Drábek Vladimír, doc. Ing., CSc. (FIT)
Mika Daniel, Ing., Ph.D.
Pečenka Tomáš, Ing., Ph.D.
Růžička Richard, doc. Ing., Ph.D., MBA (DCSY)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
Strnadel Josef, Ing., Ph.D. (DCSY)
Tupec Pavel, Ing.
Publications

2008

  • PEČENKA, T. Prostředky a metody pro automatické generování testovacích obvodů. Brno: Fakulta informačních technologií VUT v Brně, 2008. 141 s. ISBN: 978-80-214-3603-9. Detail

2006

  • BIDLO, M. Evolutionary Design Using Development. In Sborník příspěvků pracovního semináře Počítačové architektury & diagnostika pro studenty doktorského studia. Bratislava: Institute of Informatics, Slovak Academy of Sciences, 2006. p. 119-124. ISBN: 80-969202-2-7. Detail
  • ČERNÝ, S.; STRUŽKA, P.; KOŘENEK, J.; MARTÍNEK, T.; KOTÁSEK, Z. FPGA Components in Simulink. In Proceedings of XXVIIIth International Autumn Colloquium ASIS 2006. Ostrava: 2006. p. 158-163. ISBN: 80-86840-26-3. Detail
  • HERRMAN, T. Formal Model of Testable Block. In Proceedings of 12th Conference Student EEICT 2006, Volume 4. Brno: Faculty of Electrical Engineering and Communication BUT, 2006. p. 451-455. ISBN: 80-214-3163-6. Detail
  • HERRMAN, T. Metodika aplikace testu obvodu založená na identifikaci Testovatelných bloků. In Počítačové architektúry a diagnostika - zborník príspovkov. Bratislava: Ústav informatiky Slovenskej akadémie vied, 2006. s. 131-136. ISBN: 80-969202-2-7. Detail
  • HERRMAN, T. Testability Analysis Based on Formal Model. In Proceedings of the Sevnth International Scientific Conference ECI 2006. Košice: Faculty of Electrical Engineering and Informatics, University of Technology Košice, 2006. p. 243-248. ISBN: 80-8073-598-0. Detail
  • KOTÁSEK, Z.; STRNADEL, J. SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System. In Proceedings of the 13th IEEE International Symposium and Workshop on the Engineering of Computer-Based Systems (ECBS). Los Alamitos, CA: IEEE Computer Society, 2006. p. 497-498. ISBN: 0-7695-2546-6. Detail
  • MARTÍNEK, T.; LEXA, M.; KOŘENEK, J.; FUČÍK, O. A flexible technique for the automatic design of approximate string matching architectures. In Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006. p. 83-84. ISBN: 1-4244-0184-4. Detail
  • PEČENKA, T. Prostředky a metody pro automatické vytváření testovacích obvodů. In Sborník příspěvků pracovního semináře Počítačové architektury & diagnostika pro studenty doktorského studia. Bratislava: Ústav informatiky Slovenskej akadémie vied, 2006. s. 13-18. ISBN: 80-969202-2-7. Detail
  • PEČENKA, T.; KOTÁSEK, Z.; SEKANINA, L. FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Testability Properties. In Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006. p. 285-289. ISBN: 1424401844. Detail
  • PEČENKA, T.; STRNADEL, J.; KOTÁSEK, Z.; SEKANINA, L. Testability Estimation Based on Controllability and Observability Parameters. In Proceedings of the 9th EUROMICRO Conference on Digital System Design (DSD'06). IEEE CS. Cavtat: IEEE Computer Society, 2006. p. 504-514. ISBN: 0-7695-2609-8. Detail
  • RŮŽIČKA, R. DFT Flow for RT Level Digital Circuits Using iFCoRT System. In Proceedings of the Seventh International Scientific Conference Electronic Computers and Informatics ECI 2006. Košice: 2006. p. 292-297. ISBN: 80-8073-598-0. Detail
  • SEKANINA, L. Evolutionary Design of Digital Circuits: Where Are Current Limits?. In Proc. of the 1st NASA/ESA Conference on Adaptive Hardware and Systems. Piscataway: IEEE Computer Society, 2006. p. 171-178. ISBN: 0-7695-2614-4. Detail
  • SEKANINA, L.; VAŠÍČEK, Z. On the Practical Limits of the Evolutionary Digital Filter Design at the Gate Level. In Applications of Evolutionary Computing. LNCS 3907. Berlin: Springer Verlag, 2006. p. 344-355. ISBN: 978-3-540-33237-4. Detail
  • ŠKARVADA, J. GA Based Test Scheduling Under Power Constraints. In Proceedings of 12th Conference Student EEICT 2006, Volume 4. Brno: Faculty of Electrical Engineering and Communication BUT, 2006. p. 461-465. ISBN: 80-214-3163-6. Detail
  • ŠKARVADA, J. Optimalizace plánování testu číslicových systémů vzhledem k příkonu. In Sborník příspěvků pracovního semináře Počítačové architektury & diagnostika pro studenty doktorského studia. Bratislava: Ústav informatiky Slovenskej akadémie vied, 2006. s. 143-148. ISBN: 80-9692-0227. Detail
  • ŠKARVADA, J. Test Scheduling for SOC under Power Constraints. In Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Prague: Czech Technical University Publishing House, 2006. p. 91-93. ISBN: 1-4244-0184-4. Detail
  • ŠKARVADA, J.; KOTÁSEK, Z. Systém pro podporu vzdělávání v oblasti plánování testu vestavěných systémů. In Pedagogický software 2006. České Budějovice: Scientifik Pedagogical Publishing, 2006. s. 319-321. ISBN: 80-85645-56-4. Detail
  • ŠKARVADA, J.; RŮŽIČKA, R. Using Petri Nets for RT Level Digital Systems Test Scheduling. In Proceedings of 1st International Workshop on Formal Models (WFM'06). Ostrava: 2006. p. 79-86. ISBN: 80-86840-20-4. Detail
  • STRNADEL, J. On Distribution of Testability Values in Scan-Layout State-Space. In Proceedings of the 7th International Scientific Conference on Electronic Computers and Informatics. Košice: The University of Technology Košice, 2006. p. 308-313. ISBN: 80-8073-598-0. Detail
  • STRNADEL, J. Power-Constrained, Sessionless SOC Test Scheduling Based on Exploration of I-Schedule State-Space. In Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Prague: Czech Technical University Publishing House, 2006. p. 161-162. ISBN: 1-4244-0184-4. Detail
  • STRNADEL, J. Testability Analysis and Improvements of Register-Transfer Level Digital Circuits. Computing and Informatics, 2006, vol. 25, no. 5, p. 441-464. ISSN: 1335-9150. Detail

2005

  • BIDLO, M. A Developmental Method for Construction of Arbitrarily Large Sorting Networks and Adders. Brno: Faculty of Information Technology BUT, 2005. p. 1 ( p.) Detail
  • BIDLO, M. A Benchmark for the Sorting Network Problem. In Proc. of Genetic and Evolutionary Computation Conference - Workshops 2005. New York: Association for Computing Machinery, 2005. p. 289-291. ISBN: 1-59593-097-3. Detail
  • BIDLO, M. Využití modelů ontogeneze v evolučním návrhu číslicových obvodů. In Sborník příspevků ze semináře Počítačové Architektury & Diagnostika. Praha: České vysoké učení technické, 2005. s. 13-18. ISBN: 80-01-03298-1. Detail
  • BIDLO, M., SEKANINA, L. Providing Information from the Environment for Growing Electronic Circuits Through Polymorphic Gates. In Proc. of Genetic and Evolutionary Computation Conference - Workshops 2005. New York: Association for Computing Machinery, 2005. p. 242-248. ISBN: 1-59593-097-3. Detail
  • DRÁBEK, V.; KOTÁSEK, Z. Handbook of Testing Electronic Systems. In Handbook of Testing Electronic Systems. Praha: Czech Technical University Publishing House, 2005. p. 235-243. ISBN: 80-01-03318-X. Detail
  • HERRMAN, T. Metody aplikace testu založené na testovatelných jádrech. In Počítačové architektury & diagnostika 2005. Praha: České vysoké učení technické, 2005. s. 51-54. ISBN: 80-01-03298-1. Detail
  • KOTÁSEK, Z., STRNADEL, J. Testing Tools for Training and Education. In Proceedings of 12th International Conference on Mixed Design of Integrated Circuits and Systems. Krakow: Department of Microelectronics and Computer Science, Technical University of Lodz, 2005. p. 671-676. ISBN: 83-919289-9-3. Detail
  • KOTÁSEK, Z., STRNADEL, J., PEČENKA, T. Methodology of Selecting Scan-Based Testability Improving Technique. In Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005. p. 186-189. ISBN: 963-9364-48-7. Detail
  • KUBEK, J. Analýza softcore IP jader založených na konečných automatech. In Počítačové architektury & diagnostika 2005. Praha: České vysoké učení technické, 2005. s. 107-112. ISBN: 80-01-03298-1. Detail
  • PEČENKA, T. At-speed testování spojů na kartě COMBO6. In Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005. p. 221-223. ISBN: 963-9364-48-7. Detail
  • PEČENKA, T. Prostředky a metody pro automatické vytváření testovacích obvodů. In Sborník příspěvků ze semináře Počítačové Architektury a Diagnostika. Praha: Fakulta elektrotechniky ČVUT, 2005. s. 135-140. ISBN: 80-01-03298-1. Detail
  • PEČENKA, T., KOTÁSEK, Z., SEKANINA, L., STRNADEL, J. Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. In Proc. of the 2005 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2005. p. 51-58. ISBN: 0-7695-2399-4. Detail
  • RŮŽIČKA, R. On the Petri Net Based Test Scheduling. In Proceedings of the Work in Progress Session at Euromicro SEAA/DSD 2005. Linz: Johannes Kepler University Linz, 2005. p. 18-19. ISBN: 3-902457-09-0. Detail
  • SEKANINA, L. Design Methods for Polymorphic Digital Circuits. In Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005. p. 145-150. ISBN: 9639364487. Detail
  • SEKANINA, L., ZEBULUM, R. Intrinsic Evolution of Controllable Oscillators in FPTA-2. In Evolvable Systems: From Biology to Hardware. Berlin: Springer Verlag, 2005. p. 98-107. ISBN: 978-3-540-28736-0. Detail
  • ŠKARVADA, J. Plánování testu vestavěných systémů zohledňující příkon elektrické energie. In Sborník příspevků ze semináře Počítačové Architektury & Diagnostika. Praha: České vysoké učení technické, 2005. s. 147-151. ISBN: 80-01-03298-1. Detail
  • STRNADEL, J. VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements. In Proceedings of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop. Sopron: University of West Hungary, 2005. p. 190-193. ISBN: 963-9364-48-7. Detail
  • STRNADEL, J., KOTÁSEK, Z. Educational Tool for the Demonstration of Dft Principles Based on Scan Methodologies. In Proceedings of 8th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2005. p. 420-427. ISBN: 0-7695-2433-8. Detail
  • ŽÁDNÍK, M., PEČENKA, T., KOŘENEK, J. NetFlow Probe for High-Speed Networks. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL05). Tampere: IEEE Computer Society, 2005. p. 695-698. ISBN: 0-7803-9362-7. Detail

2004

  • KOTÁSEK, Z. Survey of Partial Scan Methodologies. In Research and Training Action for System on Chip Design, 5th FP Project. Bratislava: Slovak Academy of Science, 2004. p. 1 ( p.) Detail
  • KOTÁSEK, Z., MIKA, D., STRNADEL, J. The Identification of Registers in RTL Structures. In Preliminary Proceedings of 1st International Symposium on Leveraging Applications of Formal Methods ISOLA 2004. Technical Report TR-2004-6. Nicosia: Department of Computer Science of University of Cyprus, 2004. p. 317-320. ISBN: 3-540-41613. Detail
  • KOTÁSEK, Z., PEČENKA, T., STRNADEL, J., MIKA, D., SEKANINA, L. An Overview of Research Activities in Digital Circuit Diagnosis and Benchmarking. In Proceedings of the Sixth Internation Scientific Conference Electronic Computers nad Informatics 2004. Košice: The University of Technology Košice, 2004. p. 229-234. ISBN: 80-8073-150-0. Detail
  • MIKA, D. Uplatnění formálních postupů při návrhu řadiče testu číslicového obvodu. In Počítačové architektúry & diagnostika PAD 2004. Bratislava: Slovenská akademie věd, 2004. s. 144-149. ISBN: 80-969202-0-0. Detail
  • PEČENKA, T. Evoluční návrh testovacích obvodů. In Zborník príspevkov ze seminara Počítačové Architektury a Diagnostika. Bratislava: Slovenská akademie věd, 2004. s. 22-24. ISBN: 80-969202-0-0. Detail
  • PEČENKA, T., KOTÁSEK, Z., SEKANINA, L., STRNADEL, J. Evolutionary Design of Synthetic RTL Benchmark Circuits. In Informal Digest of Papers, IEEE European Test Workshop 2004. Montpellier: IEEE Computer Society, 2004. p. 107-108. ISBN: 000000000. Detail
  • PEČENKA, T., KOTÁSEK, Z., STRNADEL, J. Improving Testability Parameters of Pipelined Circuits Through the Identification of Testable Cores. In Proc. of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Bratislava: Slovak Academy of Science, 2004. p. 99-104. ISBN: 80-969117-9-1. Detail
  • RŮŽIČKA, R., SEKANINA, L. A Platform for Demonstration of Analogue and Digital Circuits Evolution. In Proceedings of the Sixth Internation Scientific Conference Electronic Computers nad Informatics 2004. Košice: The University of Technology Košice, 2004. p. 158-163. ISBN: 80-8073-150-0. Detail
  • RŮŽIČKA, R., ŠKARVADA, J. RTL Testability Verification System. In Proceedings of the Work In Progress Session of 30th Euromicro Conference. Linz: Johannes Kepler University Linz, 2004. p. 101-102. ISBN: 3-902457-05-8. Detail
  • RŮŽIČKA, R., TUPEC, P. Formal Approach to Synthesis of a Test Controller. In Proceedings of Eleventh International Conference and Workshop on the Engineering of Computer-Based Systems. Los Alamitos, California: IEEE Computer Society, 2004. p. 348-355. ISBN: 0-7695-2125-8. Detail
  • SEKANINA, L. Evolutionary Design Space Exploration for Median Circuits. Lecture Notes in Computer Science, 2004, vol. 2004, no. 3005, p. 240-249. ISSN: 0302-9743. Detail
  • SEKANINA, L. Evolvable computing by means of evolvable components. Natural Computing, 2004, vol. 3, no. 3, p. 323-355. ISSN: 15677818. Detail
  • SEKANINA, L., FRIEDL, Š. An Evolvable Combinational Unit for FPGAs. Computing and Informatics, 2004, vol. 23, no. 5, p. 461-486. ISSN: 1335-9150. Detail
  • VAŠÍČEK, Z., SEKANINA, L. Evoluční návrh kombinačních obvodů. Elektrorevue - Internetový časopis (http://www.elektrorevue.cz), 2004, roč. 2004, č. 43, s. 1-6. ISSN: 1213-1539. Detail
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