Publication Details

Acceleration of Functional Verification in the Development Cycle of Hardware Systems

ZACHARIÁŠOVÁ, M. Acceleration of Functional Verification in the Development Cycle of Hardware Systems. Počítačové architektury a diagnostika. Praha: Czech Technical University, 2012. p. 73-78. ISBN: 978-80-01-05106-1.

Czech title

Využití akcelerace funkční verifikaci při vývoji hardwarových systémů

Type

conference paper

Language

English

Authors

Zachariášová Marcela, Ing., Ph.D. (DCSY)

Keywords

functional verification, hardware acceleration, genetic algorithm, optimization

Abstract

Functional verification is a widespread technique for checking whether a hardware system satisfies a given correctness specification. The complexity of modern computer systems is rapidly rising and the verification process takes significant amount of time. It is a challenging process to find appropriate acceleration techniques. I introduce a strategy for acceleration of functional verification using FPGAs by targeting special components of the verification environment to the FPGA.The second approach utilizes genetic algorithm in order to optimize and automate a technique called coverage-driven verification.

Published

2012

Pages

73–78

Proceedings

Počítačové architektury a diagnostika

ISBN

978-80-01-05106-1

Publisher

Czech Technical University

Place

Praha

BibTeX

@inproceedings{BUT97039,
  author="Marcela {Zachariášová}",
  title="Acceleration of Functional Verification in the Development Cycle of Hardware Systems",
  booktitle="Počítačové architektury a diagnostika",
  year="2012",
  pages="73--78",
  publisher="Czech Technical University",
  address="Praha",
  isbn="978-80-01-05106-1"
}