Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration

Czech title

Metodologie pro návrh systémů s vysokou spolehlivostí do FPGA

Type

conference paper

Language

English

Authors

Kaštil Jan, Ing., Ph.D.
Straka Martin, Ing., Ph.D.
Kotásek Zdeněk, doc. Ing., CSc.

Keywords

FPGA, partial dynamic reconfiguration, reliability, redundancy, checker, SEU, controller

Abstract

In the paper, the activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. The methodology supports the detection a localization of all soft errors in the design and recovery mechanism which is based on the principles of partial dynamic reconfiguration of the chip. The main features of methodology are presented in the paper.

Annotation

In the paper, the activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. The methodology supports the detection a localization of all soft errors in the design and recovery mechanism which is based on the principles of partial dynamic reconfiguration of the chip. The main features of methodology are presented in the paper.

Published

2012

Pages

1–4

Proceedings

The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12)

Publisher

Politecnico di Milano

Place

Annecy

BibTeX

@inproceedings{BUT91473,
  author="Jan {Kaštil} and Martin {Straka} and Zdeněk {Kotásek}",
  title="Methodology for Increasing Reliability of FPGA Design via Partial Reconfiguration",
  booktitle="The First Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN'12)",
  year="2012",
  pages="1--4",
  publisher="Politecnico di Milano",
  address="Annecy"
}