Publication Details

Hardware Accelerated Functional Verification

ZACHARIÁŠOVÁ, M. Hardware Accelerated Functional Verification. Proceedings of the 17th Conference STUDENT EEICT 2011. Brno: Faculty of Information Technology BUT, 2011. p. 321-323. ISBN: 978-80-214-4272-6.
Czech title
Hardwarově akcelerovaná funkční verifikace
Type
conference paper
Language
English
Authors
Zachariášová Marcela, Ing., Ph.D. (DCSY)
URL
Keywords

functional verification, testbench, SystemVerilog, hardware acceleration, FPGA

Abstract

Functional verification is a widespread technique for checking whether a hardware system satisfies a given correctness specification. The complexity of modern computer systems is rapidly rising and the verification process takes significant amount of time. It is a challenging process to find appropriate acceleration techniques. We introduce a strategy for acceleration of functional verification using FPGAs by targeting special components of the verification environment to the FPGA.

Published
2011
Pages
321–323
Proceedings
Proceedings of the 17th Conference STUDENT EEICT 2011
ISBN
978-80-214-4272-6
Publisher
Faculty of Information Technology BUT
Place
Brno
BibTeX 
@inproceedings{BUT76419,
  author="Marcela {Zachariášová}",
  title="Hardware Accelerated Functional Verification",
  booktitle="Proceedings of the 17th Conference STUDENT EEICT 2011",
  year="2011",
  pages="321--323",
  publisher="Faculty of Information Technology BUT",
  address="Brno",
  isbn="978-80-214-4272-6",
  url="http://www.feec.vutbr.cz/EEICT/2011/sbornik/02-Magisterske%20projekty/10-Pocitacove%20systemy/10-xsimko03.pdf"
}
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