Publication Details

Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units

VAŠÍČEK, Z.; SEKANINA, L. Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units. Computing and Informatics, 2010, vol. 29, no. 6, p. 1359-1371. ISSN: 1335-9150.

Czech title

Obvodový akcelerátor pro kartézské genetické programování s násobnými fitness jednotkami

Type

journal article

Language

English

Authors

Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)

Keywords

Cartesian genetic programming, hardware accelerator, evolutionary circuit design, FPGA

Abstract

A new accelerator of Cartesian genetic programming is presented in this paper. The accelerator is completely implemented in a single FPGA. The proposed architecture contains multiple instances of virtual reconfigurable circuit to evaluate several candidate solutions in parallel. An advanced memory organization was developed to achieve the maximum throughput of processing. The search algorithm is implemented using the on-chip PowerPC processor. In the benchmark problem (image filter evolution) the proposed platform provides a significant speedup (170) in comparison with a highly optimized software implementation. Moreover, the accelerator is 8 times faster than previous FPGA accelerators of image filter evolution.

Published

2010

Pages

1359–1371

Journal

Computing and Informatics, vol. 29, no. 6, ISSN 1335-9150

BibTeX

@article{BUT50732,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units",
  journal="Computing and Informatics",
  year="2010",
  volume="29",
  number="6",
  pages="1359--1371",
  issn="1335-9150",
  url="https://www.fit.vut.cz/research/publication/9421/"
}