Publication Details

Efficient Hardware Accelerator for Symbolic Regression Problems

VAŠÍČEK, Z.; SEKANINA, L. Efficient Hardware Accelerator for Symbolic Regression Problems. 5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Znojmo: Masaryk University, 2009. p. 192-199. ISBN: 978-80-87342-04-6.
Czech title
Efektivní hardwarový akcelerátor pro řešení problému symbolické regrese
Type
conference paper
Language
English
Authors
Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
Keywords

hardware acceleration, regression problem, evolutionary design, image filter, fpga, powerpc

Abstract

In this paper, a new hardware architecture for the acceleration of symbolic regression problems using Cartesian Genetic Programming (CGP) is presented. In order to minimize the number of expensive memory accesses, a new algorithm is proposed. The search algorithm is implemented using PowerPC processor which is available in Xilinx FPGAs of Virtex family. A significant speedup of evolution is obtained in comparison with a highly optimized software implementation of CGP.

Published
2009
Pages
192–199
Proceedings
5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
ISBN
978-80-87342-04-6
Publisher
Masaryk University
Place
Znojmo
BibTeX 
@inproceedings{BUT34289,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="Efficient Hardware Accelerator for Symbolic Regression Problems",
  booktitle="5th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
  year="2009",
  pages="192--199",
  publisher="Masaryk University",
  address="Znojmo",
  isbn="978-80-87342-04-6",
  url="https://www.fit.vut.cz/research/publication/9108/"
}
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