Publication Details

Physical Demonstration of Polymorphic Self-checking Circuits

RŮŽIČKA, R.; SEKANINA, L.; PROKOP, R. Physical Demonstration of Polymorphic Self-checking Circuits. Proc. of the 14th IEEE Int. On-Line Testing Symposium. Los Alamitos: IEEE Computer Society, 2008. p. 31-36. ISBN: 978-0-7695-3264-6.
Czech title
Physical Demonstration of Polymorphic Self-checking Circuits
Type
conference paper
Language
English
Authors
Růžička Richard, doc. Ing., Ph.D., MBA (DCSY)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
Prokop Roman, Ing., Ph.D. (UMEL)
Keywords

digital circuit, polymorphic gate, self-checking, adder

Abstract

Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized in a self-checking polymorphic adder. This paper presents an experimental evaluation of this novel implementation.

Published
2008
Pages
31–36
Proceedings
Proc. of the 14th IEEE Int. On-Line Testing Symposium
ISBN
978-0-7695-3264-6
Publisher
IEEE Computer Society
Place
Los Alamitos
BibTeX 
@inproceedings{BUT30488,
  author="Richard {Růžička} and Lukáš {Sekanina} and Roman {Prokop}",
  title="Physical Demonstration of Polymorphic Self-checking Circuits",
  booktitle="Proc. of the 14th IEEE Int. On-Line Testing Symposium",
  year="2008",
  pages="31--36",
  publisher="IEEE Computer Society",
  address="Los Alamitos",
  isbn="978-0-7695-3264-6",
  url="https://www.fit.vut.cz/research/publication/8652/"
}
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