Publication Details

VHDL Design of Educational, Modern and Open-Architecture CPU

STRAKA, M. VHDL Design of Educational, Modern and Open-Architecture CPU. In Proceedings of the 13th Conference STUDENT EEICT 2007 Volume 4. Brno: Brno University of Technology, 2007. p. 457-461. ISBN: 978-80-214-3410-3.

Czech title

Návrh pokročilé architektury procesoru ve VHDL

Type

conference paper

Language

English

Authors

Straka Martin, Ing., Ph.D.

Keywords

VHDL, pipeline, CPU, cache, prediction unit

Abstract

The paper deals with design of a modern, open-architecture CPU utilizable for educational purposes. It is expected that use of the CPU in the educational process will greatly contribute to deeper understanding of key-topics taught in the area of modern architectures. Our CPU is based on the Von-Neumann architecture, equipped with a five-stage pipeline, cache memory unit and simple branch prediction unit. The architecture is designed in VHDL including set of 16 instructions. Rich variety of educative tasks can be performed by means of the CPU. It has been both successfully simulated in ModelSim and synthesized in Precision RTL Synthesis in order to be implemented in FPGA and utilized in practice as a real working CPU.

Published

2007

Pages

457–461

Proceedings

Proceedings of the 13th Conference STUDENT EEICT 2007 Volume 4

Conference

Student EEICT 2007, Brno, CZ

ISBN

978-80-214-3410-3

Publisher

Brno University of Technology

Place

Brno

BibTeX

@inproceedings{BUT28605,
  author="Martin {Straka}",
  title="VHDL Design of Educational, Modern and Open-Architecture CPU",
  booktitle="Proceedings of the 13th Conference STUDENT EEICT 2007 Volume 4",
  year="2007",
  pages="457--461",
  publisher="Brno University of Technology",
  address="Brno",
  isbn="978-80-214-3410-3"
}