Detail publikace

VHDL Design of Educational, Modern and Open-Architecture CPU

STRAKA, M. VHDL Design of Educational, Modern and Open-Architecture CPU. In Proceedings of the 13th Conference STUDENT EEICT 2007 Volume 4. Brno: Brno University of Technology, 2007. p. 457-461. ISBN: 978-80-214-3410-3.

Název česky

Návrh pokročilé architektury procesoru ve VHDL

Typ

článek ve sborníku konference

Jazyk

anglicky

Autoři

Straka Martin, Ing., Ph.D.

Klíčová slova

VHDL, pipeline, CPU, cache, prediction unit

Abstrakt

Návrh pokročilé architektury procesoru ve VHDL

Rok

2007

Strany

457–461

Sborník

Proceedings of the 13th Conference STUDENT EEICT 2007 Volume 4

Konference

Student EEICT 2007, Brno, CZ

ISBN

978-80-214-3410-3

Vydavatel

Brno University of Technology

Místo

Brno

BibTeX

@inproceedings{BUT28605,
  author="Martin {Straka}",
  title="VHDL Design of Educational, Modern and Open-Architecture CPU",
  booktitle="Proceedings of the 13th Conference STUDENT EEICT 2007 Volume 4",
  year="2007",
  pages="457--461",
  publisher="Brno University of Technology",
  address="Brno",
  isbn="978-80-214-3410-3"
}