Detail publikace

Digital Systems Architectures Based on On-line Checkers

STRAKA, M.; KOTÁSEK, Z.; WINTER, J. Digital Systems Architectures Based on On-line Checkers. 11th EUROMICRO Conference on Digital System Design DSD 2008. Parma: IEEE Computer Society, 2008. p. 81-87. ISBN: 978-0-7695-3277-6.
Název česky
Digital Systems Architectures Based on On-line Checkers
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Straka Martin, Ing., Ph.D.
Kotásek Zdeněk, doc. Ing., CSc.
Winter Jan, Ing.
Klíčová slova

Fault Tolerant Systems, simple circuit, checker, FPGA, on-line testing, protocols

Abstrakt

In this paper, we present a methodology for generating VHDL descriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line checkers of communication protocols, counters, decoders, registers, comparators, etc. It is also demonstrated how a checker for more complex structures can be developed. We describe the possibilities of utilizing this approach in the design of Fault Tolerant Systems (FTS). Experimental results in terms of FPGA resources needed to synthesize different types of checkers are presented.

Rok
2008
Strany
81–87
Sborník
11th EUROMICRO Conference on Digital System Design DSD 2008
ISBN
978-0-7695-3277-6
Vydavatel
IEEE Computer Society
Místo
Parma
BibTeX 
@inproceedings{BUT27769,
  author="Martin {Straka} and Zdeněk {Kotásek} and Jan {Winter}",
  title="Digital Systems Architectures Based on On-line Checkers",
  booktitle="11th EUROMICRO Conference on Digital System Design DSD 2008",
  year="2008",
  pages="81--87",
  publisher="IEEE Computer Society",
  address="Parma",
  isbn="978-0-7695-3277-6",
  url="https://www.fit.vut.cz/research/publication/8621/"
}
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