Publication Details

Setup for an Experimental Study of Radiation Effects in 65nm CMOS

FRITZ, B.; STEININGER, A.; ŠIMEK, V.; VEERAVALLI, V. Setup for an Experimental Study of Radiation Effects in 65nm CMOS. In 2017 20th Euromicro Conference on Digital System Design (DSD). Vienna: IEEE Computer Society, 2017. p. 329-336. ISBN: 978-1-5386-2146-2.
Czech title
Aparatura pro experimentální analýzu radiačních efektů v 65nm CMOS technologii
Type
conference paper
Language
English
Authors
FRITZ, B.
Steininger Andreas, Prof. Dr.
Šimek Václav, Ing. (DCSY)
VEERAVALLI, V.
URL
Keywords

Integrated circuit modeling, Field programmable gate arrays, Particle beams, Radiation effects, Transistors, Atmospheric modeling, Very large scale integration

Abstract

Physical radiation experiments are a vital means for calibrating simulation models targeted to studying the impact of ionizing particles on VLSI circuits. However, their conduction requires special care and a very specific setup. In this paper we give an overview of such an experimental setup, and highlight some specific details. Beyond showing the context overarching the objectives of the experiments, the envisioned radiation sources, as well as design and architecture of a specific target ASIC, we will put specific emphasis on the communication infrastructure, namely an FPGA that controls the data exchange between some preprocessing infrastructure located on the target ASIC on one side and the host PC running the data analysis on the other. Finally, the physical arrangement comprising carrier PCB for the target ASIC, and cabling, which need to adhere specific requirements, will receive some attention as well.

Published
2017
Pages
329–336
Proceedings
2017 20th Euromicro Conference on Digital System Design (DSD)
ISBN
978-1-5386-2146-2
Publisher
IEEE Computer Society
Place
Vienna
DOI
UT WoS
000427097100046
EID Scopus
BibTeX
@inproceedings{BUT163427,
  author="FRITZ, B. and STEININGER, A. and ŠIMEK, V. and VEERAVALLI, V.",
  title="Setup for an Experimental Study of Radiation Effects in 65nm CMOS",
  booktitle="2017 20th Euromicro Conference on Digital System Design (DSD)",
  year="2017",
  pages="329--336",
  publisher="IEEE Computer Society",
  address="Vienna",
  doi="10.1109/DSD.2017.60",
  isbn="978-1-5386-2146-2",
  url="https://ieeexplore.ieee.org/document/8049805"
}
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