Publication Details

Scalable P4 Deparser for Speeds Over 100 Gbps

CABAL, J.; BENÁČEK, P.; FOLTOVÁ, J.; HOLUB, J. Scalable P4 Deparser for Speeds Over 100 Gbps. Annual IEEE Symposium on Field-Programmable Custom Computing Machines. Los Alamitos: 2019. p. 323-323. ISBN: 978-1-7281-1131-5.
Czech title
Škálování P4 deparseru při rychostech vyšších než 100 Gbps
Type
abstract
Language
English
Authors
Cabal Jakub, Ing.
Benáček Pavel
Foltová Jana, Mgr. (DCSY)
Holub Juraj, Ing.
URL
Keywords

field programmable gate arrays (FPGA), high speed networks, 100gbps, building blockes, deparser, network devices, P4 language, packet processing, packet-based, scalable architectures, computers

Abstract

The P4 language is a language suitable for the description of packet processing inside a network device. The typical P4 device consists of three main building blocks: Parser, Match+Action Tables and Deparser. The deparsing is the most challenging block because the main task of this block is to assemble the output packet based on changes in Match+Action Tables. This operation can be quite complicated in the case of high-speed networks. In this work, we present the scalable architecture (in term of the throughput) of a deparsing circuit which is suitable for implementation in FPGAs.

Published
2019
Pages
323–323
Book
Annual IEEE Symposium on Field-Programmable Custom Computing Machines
ISBN
978-1-7281-1131-5
Place
Los Alamitos
DOI
10.1109/FCCM.2019.00064
UT WoS
000491873200055
EID Scopus
2-s2.0-85068311347
BibTeX 
@misc{BUT163388,
  author="Jakub {Cabal} and Pavel {Benáček} and Jana {Foltová} and Juraj {Holub}",
  title="Scalable P4 Deparser for Speeds Over 100 Gbps",
  booktitle="Annual IEEE Symposium on Field-Programmable Custom Computing Machines",
  year="2019",
  pages="323--323",
  address="Los Alamitos",
  doi="10.1109/FCCM.2019.00064",
  isbn="978-1-7281-1131-5",
  url="https://ieeexplore.ieee.org/document/8735524",
  note="abstract"
}
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