Detail publikace

Testing PCBs Based on Boundary Scan

KOTÁSEK, Z.; TUPEC, P.; URBIŠ, H. Testing PCBs Based on Boundary Scan. Proceedings of International Carpathian Control Conference. Košice: The University of Technology Košice, 2003. p. 119-122. ISBN: 80-7099-509-2.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Kotásek Zdeněk, doc. Ing., CSc.
Tupec Pavel, Ing.
Urbiš Hynek, Ing.
Klíčová slova

Boundary Scan, PCB, FPGA

Abstrakt

The paper describes a practical approach to testing PCBs with Xilinx FPGAs. The approach is based on a PCB netlist analysis, which is revealing the existing connections on the PCB through the Boundary Scan chain and comparing the two results. It is also supposed that the developed software tools will be used for debugging PCBs with Xilinx FPGAs. The goal of the research activities is to develop an easy to use an efficient and user- friendly software tools.

Rok
2003
Strany
119–122
Sborník
Proceedings of International Carpathian Control Conference
ISBN
80-7099-509-2
Vydavatel
The University of Technology Košice
Místo
Košice
BibTeX 
@inproceedings{BUT14165,
  author="Zdeněk {Kotásek} and Pavel {Tupec} and Hynek {Urbiš}",
  title="Testing PCBs Based on Boundary Scan",
  booktitle="Proceedings of International Carpathian Control Conference",
  year="2003",
  pages="119--122",
  publisher="The University of Technology Košice",
  address="Košice",
  isbn="80-7099-509-2"
}
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