Publication Details

Hardware Architecture for the Fast Pattern Matching

KAŠTIL, J.; KOŠAŘ, V.; KOŘENEK, J. Hardware Architecture for the Fast Pattern Matching. 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Brno: IEEE Computer Society, 2013. p. 120-123. ISBN: 978-1-4673-6133-0.
Czech title
Hardwarová architektura pro rychlé vyhledávání vzorů
Type
conference paper
Language
English
Authors
Kaštil Jan, Ing., Ph.D.
Košař Vlastimil, Ing., Ph.D. (DCSY)
Kořenek Jan, doc. Ing., Ph.D. (DCSY)
Keywords

pattern matching, intrussion detection system, regular expression, FPGA

Abstract

As the speed of current computer networks in- creases, it is necessary to protect networks by security systems such as firewalls and Intrusion Detection Systems (IDS) operating at multigigabit speeds. As attacks on modern networks became more and more complex, it is necessity to detect attack placed not only in single packet but at the level of network flows. Pattern matching in the network flows is the time-critical operation of many modern IDS. Most of the regularly used patterns are described by the regular expression. This work describes advanced hardware architecture for the fast regular expression matching based on the perfect hashing. The proposed architecture is scalable and can achieve multigigabit throughput per network flow.

Published
2013
Pages
120–123
Proceedings
2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
ISBN
978-1-4673-6133-0
Publisher
IEEE Computer Society
Place
Brno
BibTeX 
@inproceedings{BUT103447,
  author="Jan {Kaštil} and Vlastimil {Košař} and Jan {Kořenek}",
  title="Hardware Architecture for the Fast Pattern Matching",
  booktitle="2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)",
  year="2013",
  pages="120--123",
  publisher="IEEE Computer Society",
  address="Brno",
  isbn="978-1-4673-6133-0"
}
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