Project Details

Metodika a prostředky pro analýzu testovatelnosti digitálních obvodů

Project Period: 1. 1. 1998 – 31. 3. 2006

Project Type: grant

Code: GA102/98/1463

Agency: Czech Science Foundation

Program: Standardní projekty

English title
Methodology and tools for digital circuits testability analysis
Type
grant
Abstract

The goal of the research activities is to develop and implement testability analysis methodology such that the concepts and algorithms could be used in any design environment, to offer an alternative to the full scan approach. It is supposed that the structure of the circuit under analysis will be transformed into a database representing the diagnostic features of the circuit. The applicability will be verified on circuits described in VHDL language and on ISCAS benchmark circuits.

Team members
Kotásek Zdeněk, doc. Ing., CSc. – research leader
Drábek Vladimír, doc. Ing., CSc. (FIT)
Fučík Otto, doc. Dr. Ing. (DCSY)
Zbořil František, doc. Ing., CSc. (DITS)
Publications

2000

  • SEKANINA, L.; DRÁBEK, V. Relation Between Fault Tolerance and Reconfiguration in Cellular Systems. 6th IEEE Int. On-Line Testing Workshop. Palma de Mallorca, Spain: IEEE Computer Society Press, 2000. p. 25-30. ISBN: 0-7695-0646-1. Detail
  • ZBOŘIL, F. VHDL RT Level Parser/Analyser of a Source Code. Proceedings of the fourth international scientific conference Electronic Computers & Informatics'2000. Košice: Faculty of Electrical Engineering and Informatics, University of Technology Košice, 2000. p. 150-155. ISBN: 80-88922-25-9. Detail

1998

  • ZBOŘIL, F., KOTÁSEK, Z. Nonstandard Automatic Test Pattern Generation Based on Neural Network Theory. In Proceedings of the ECI'98. Herlany, SR: SAV, 1998. p. 75-80. ISBN: 80-88786-94-0. Detail
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