Project Details

Metody návrhu polymorfních číslicových obvodů

Project Period: 1. 1. 2006 – 31. 12. 2008

Project Type: grant

Code: GA102/06/0599

Agency: Czech Science Foundation

Program: Standardní projekty

English title
Methods of polymorphic digital circuit design
Type
grant
Keywords

computer science; digital circuit design; evolutionary algorithm

Abstract

This is a multidisciplinary project of artificial intelligence and microelectronics in a new area of research called polymorphic electronics. Polymorphic circuits are circuits that are able to implement various useful functions in various environments (e.g. to implement addition at a given temperature and multiplication at another temperature). However, no functional switch is used; they are multifunctional in principle. The objective of this project is to propose methods for routine designing of nontrivial polymorphic digital circuits and to utilize polymorphic circuits in real-world applications whose implementation is impossible or difficult by means of conventional methods. Polymorphic gates will be considered as basic building blocks for implementation of polymorphic circuits. New evolutionary-based design methods will be developed operating at the polymorphic gate level. We will design and implement an integrated circuit consisting of polymorphic gates. This project was formulated on the basis of our long-term experience in evolutionary electronics and digital circuit design.

Team members
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY) – research leader
Bidlo Michal, doc. Ing., Ph.D. (DCSY)
Drábek Vladimír, doc. Ing., CSc. (FIT)
Gajda Zbyšek, Ing., Ph.D. (RG EHW)
Kotásek Zdeněk, doc. Ing., CSc.
Musil Vladislav, prof. Ing., CSc.
Prokop Roman, Ing., Ph.D. (UMEL)
Růžička Richard, doc. Ing., Ph.D., MBA (DCSY)
Stareček Lukáš, Ing., Ph.D. (RG EHW)
Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY)
Publications

2009

  • GAJDA, Z.; SEKANINA, L. Gate-Level Optimization of Polymorphic Circuits Using Cartesian Genetic Programming. Proc. of 2009 IEEE Congress on Evolutionary Computation. NA: IEEE Computational Intelligence Society, 2009. p. 1599-1604. ISBN: 978-1-4244-2958-5. Detail
  • SEKANINA, L.; RŮŽIČKA, R.; VAŠÍČEK, Z.; PROKOP, R.; FUJCIK, L. REPOMO32 - New Reconfigurable Polymorphic Integrated Circuit for Adaptive Hardware. Proc. of the 2009 IEEE Symposium Series on Computational Intelligence - Workshop on Evolvable and Adaptive Hardware. Nashville: IEEE Computational Intelligence Society, 2009. p. 39-46. ISBN: 978-1-4244-2755-0. Detail
  • SEKANINA, L.; VAŠÍČEK, Z.; RŮŽIČKA, R.; BIDLO, M.; JAROŠ, J.; ŠVENDA, P. Evoluční hardware: Od automatického generování patentovatelných invencí k sebemodifikujícím se strojům. Edice Gerstner. Edice Gerstner. Praha: Nakladatelství Academia, 2009. 328 s. ISBN: 978-80-200-1729-1. Detail

2008

  • BIDLO, M.; VAŠÍČEK, Z. Cellular Automata-Based Development of Combinational and Polymorphic Circuits: A Comparative Study. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2008. p. 106-117. ISBN: 978-3-540-85856-0. Detail
  • GAJDA, Z. Návrh polymorfních obvodů. Počítačové architektury a diagnostika 2008. Liberec: Technická univerzita v Liberci, 2008. s. 17-23. ISBN: 978-80-7372-378-1. Detail
  • RŮŽIČKA, R. On Bifunctional Polymorphic Gates Controlled by a Special Signal. WSEAS Transactions on Circuits, 2008, vol. 7, no. 3, p. 96-101. ISSN: 1109-2734. Detail
  • RŮŽIČKA, R.; PROKOP, R. Bifunctional NAND/NOR Gates as Building Blocks for Polytronics. Proceedings of CSE 2008. Stará Lesná: The University of Technology Košice, 2008. p. 200-207. ISBN: 978-80-8086-092-9. Detail
  • RŮŽIČKA, R.; SEKANINA, L.; PROKOP, R. Physical Demonstration of Polymorphic Self-checking Circuits. Proc. of the 14th IEEE Int. On-Line Testing Symposium. Los Alamitos: IEEE Computer Society, 2008. p. 31-36. ISBN: 978-0-7695-3264-6. Detail
  • SEKANINA, L.; MIKUŠEK, P. Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures. Applications of Evolutionary Computing. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2008. p. 144-153. ISBN: 978-3-540-78760-0. Detail
  • SEKANINA, L.; STAREČEK, L.; KOTÁSEK, Z.; GAJDA, Z. Polymorphic Gates in Design and Test of Digital Circuits. International Journal of Unconventional Computing, 2008, vol. 4, no. 2, p. 125-142. ISSN: 1548-7199. Detail
  • STAREČEK, L.; SEKANINA, L.; KOTÁSEK, Z. Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: IEEE Computer Society, 2008. p. 255-258. ISBN: 978-1-4244-2276-0. Detail
  • VAŠÍČEK, Z.; ČAPKA, L.; SEKANINA, L. Analysis of Reconfiguration Options for a Reconfigurable Polymorphic Circuit. Proc. of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2008. p. 3-10. ISBN: 978-0-7695-3166-3. Detail
  • ŽALOUDEK, L.; SEKANINA, L. Transistor-level Evolution of Digital Circuits Using a Special Circuit Simulator. Evolvable Systems: From Biology to Hardware. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2008. p. 320-331. ISBN: 978-3-540-85856-0. Detail

2007

  • BIDLO, M. Evolutionary Development of Generic Multipliers: Initial Results. In Proc. of the 2007 NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society, 2007. p. 405-412. ISBN: 0-7695-2866-X. Detail
  • BRYAN, L.; FUČÍK, O.; DRÁBEK, V. HW-Based Object Detection Method for Traffic Monitoring. In 6th Electronic Circuits and Systems Conference (ECS 2007). Bratislava: Faculty of Electrical Engineering and Information Technology, Slovak University of Technology in Bratislava, 2007. p. 93-96. ISBN: 978-80-227-2697-9. Detail
  • DRÁBEK, V. Hardware Unit for Motion Estimation. In Electronic Devices and Systems. Brno: Faculty of Electrical Engineering and Communication BUT, 2007. p. 17-21. ISBN: 978-80-214-3470-7. Detail
  • DRÁBEK, V. The Evolution of Graphical Processors. In 6th Electronic Circuits and Systems Conference (ECS 2007). Bratislava: Faculty of Informatics and Information Technology STU, 2007. p. 97-102. ISBN: 978-80-227-2697-9. Detail
  • GAJDA, Z. Metody návrhu polymorfních obvodů. In Sborník příspěvků Česko-slovenského semináře Počítačové architektury a diagnostika pro studenty doktorandského studia. Plzeň: Západočeská univerzita v Plzni, 2007. s. 19-25. ISBN: 978-80-7043-605-9. Detail
  • RŮŽIČKA, R. New Polymorphic NAND/XOR Gate. In Proceedings of 7th WSEAS International Conference on Applied Computer Science. WSEAS Applied Informatics & Communications. Computer Science Challenges. Venice: World Scientific and Engineering Academy, 2007. p. 192-196. ISBN: 978-960-6766-15-2. ISSN: 1790-5117. Detail
  • RŮŽIČKA, R.; STAREČEK, L. Development of Building Blocks for Polymorphic Digital Circuits. In Proceedings of the Work in Progress Session of 10th Euromicro DSD 2007. Linz: Johannes Kepler University Linz, 2007. p. 33-34. ISBN: 978-3-902457-16-5. Detail
  • SEKANINA, L. Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates. In 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Gliwice: IEEE Computer Society, 2007. p. 243-246. ISBN: 1424411610. Detail
  • SEKANINA, L. Evolution of Polymorphic Self-Checking Circuits. In Evolvable Systems: From Biology to Hardware. LNCS 4684. Berlin: Springer Verlag, 2007. p. 186-197. ISBN: 978-3-540-74625-6. Detail
  • SEKANINA, L. Evolutionary Functional Recovery in Virtual Reconfigurable Circuits. ACM Journal on Emerging Technologies in Computing Systems, 2007, vol. 3, no. 2, p. 1-22. ISSN: 1550-4832. Detail
  • STAREČEK, L. Polymorfní hradla pro optimalizaci testu obvodu. In Sborník příspěvků Česko-slovenského semináře Počítačové architektury a diagnostika pro studenty doktorandského studia. Plzeň: Západočeská univerzita v Plzni, 2007. s. 41-46. ISBN: 978-80-7043-605-9. Detail
  • STAREČEK, L.; SEKANINA, L.; GAJDA, Z.; KOTÁSEK, Z.; PROKOP, R.; MUSIL, V. On Properties and Utilization of Some Polymorphic Gates. In 6th Electronic Circuits and Systems Conference (ECS 2007). Bratislava: Faculty of Informatics and Information Technology STU, 2007. p. 77-81. ISBN: 978-80-227-2697-9. Detail

2006

  • BIDLO, M.; BIDLO, R.; SEKANINA, L. Designing a Novel General Sorting Network Constructor Using Artificial Evolution. Transactions on Engineering, Computing and Technology, 2006, vol. 15, no. 10, p. 85-90. ISSN: 1305-5313. Detail
  • GAJDA, Z. A Core Generator for Multi-ALU Processors Utilized in Genetic Parallel Programming. In Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006. p. 238-240. ISBN: 1424401844. Detail
  • GAJDA, Z. Návrh polymorfních obvodů. In Sborník příspěvků pracovního semináře Počítačové architektury & diagnostika pro studenty doktorského studia. Bratislava: Ústav informatiky Slovenskej akadémie vied, 2006. s. 55-60. ISBN: 80-969202-2-7. Detail
  • OČENÁŠEK, J.; CANTÚ-PAZ, E.; PELIKÁN, M.; SCHWARZ, J. Design of Parallel Estimation of Distribution Algorithms. In Scalable Optimization via Probabilistic Modeling. Studies in Computational Intelligence. Berlin: Springer Verlag, 2006. p. 187-201. ISBN: 978-3-540-34953-2. Detail
  • RŮŽIČKA, R.; SEKANINA, L. Evolutionary Circuit Design in REPOMO - Reconfigurable Polymorphic Module. In Proceedings of the Second IASTED International Conference on Computational Intelligence. Anaheim: ACTA Press, 2006. p. 237-241. ISBN: 0-88986-602-3. Detail
  • SEKANINA, L. On Dependability of FPGA-Based Evolvable Hardware Systems That Utilize Virtual Reconfigurable Circuits. In Computing Frontiers 2006 Conference. New York: Association for Computing Machinery, 2006. p. 221-228. ISBN: 1595933026. Detail
  • SEKANINA, L.; MARTÍNEK, T.; GAJDA, Z. Extrinsic and Intrinsic Evolution of Multifunctional Combinational Modules. In 2006 IEEE World Congress on Computational Intelligence. CA: IEEE Computational Intelligence Society, 2006. p. 9676-9683. ISBN: 0-7803-9489-5. Detail
  • SEKANINA, L.; STAREČEK, L.; GAJDA, Z.; KOTÁSEK, Z. Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage. In Proc. of the 1st NASA/ESA Conference on Adaptive Hardware and Systems. Piscataway: IEEE Computer Society, 2006. p. 186-193. ISBN: 0-7695-2614-4. Detail
  • SEKANINA, L.; STAREČEK, L.; KOTÁSEK, Z. Novel Logic Circuits Controlled by Vdd. In Proc. of 2006 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Praha: IEEE Computer Society, 2006. p. 85-86. ISBN: 1424401844. Detail
  • ŠIMEK, V.; POKORNÝ, P. Communication of sensor modules. In Proceedings of the 12th konference Student EEICT 2006. Volume II. Brno: Faculty of Electrical Engineering and Communication BUT, 2006. p. 56-58. ISBN: 80-214-3161-X. Detail
  • STAREČEK, L. Modelování polymorfních hradel a obvodů. In Sborník příspěvků Česko-slovenského semináře Počítačové architektury a diagnostika pro studenty doktorandského studia. Bratislava: Slovenská akademie věd, 2006. s. 67-72. ISBN: 80-969202-2-7. Detail
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