VHDL Seminar

• 26 hrs seminar
• 13 hrs projects

• 100 pts projects

To give the students the knowledge of syntax and semantics of hardware description language VHDL, its use for modelling, simulation, and synthesis of complex digital systems, as well as the skills in VHDL programming techniques and the use of professional design tools.
The student should be able to describe and simulate complex digital systems using VHLD language constructs including both behavioural and structural description. This course is recommended as a co-requisite for INC and INP.

Basic skills in programming and digital design, fundamentals of Boolean algebra.

• Jasinski, R.: Effective Coding with VHDL: Principles and Best Practice. The MIT Press. 2016.
• Pedroni, V. A.: Circuit Design and Simulation with VHDL (Second Edition). The MIT Press. 2011
• Armstrong, J.R. - Gray, F.G.: VHDL Design Representation and Synthesis, 2nd edition, Prentice Hall, ISBN 0-13-021670-4, 2000
• Chang, K.C.: Digital Design and Modeling with VHDL and Synthesis, IEEE Computer Society Press, 1997
• Armstrong, J.R. - Gray F.G.: Structured Logic Design with VHDL, Prentice-Hall, 1993

1. Modern hardware design (design flow), hardware description languages (VHDL, Verilog), FPGA, introduction to digital systems.
2. Basic VHDL language structure, lexical description, VHDL source code.
3. Data types, data objects, object classes, data object declaration.
4. VHDL language statements
5. Advanced VHDL language properties, time delay and scheduling.
6. Combination circuits description, three-state circuits.
7. Synchronous sequential circuits description, finite state automata description, asynchronous sequential circuits.
8. Circuits modeling and event based simulation, circuit testing, test design, functional simulation (ModelSIM), co-simulation.
9. Circuit synthesis, constraints, synthesis for FPGA, time simulation.
10. Advanced methods (pipelining, retiming, component sharing, flattening and structuring)
11. Complex circuit case study: LED matrix display, UART, ETHERNET
12. Complex circuit case study: RISC processor
13. FPGA circuits, mass parallelism in cryptography (RC4, DES), DNA-alignment

Individual project dividend into several parts.

Project supported by the written technical report in the English language. Exam prerequisites: Class credit is gained when a minimum total score of 50% points is gained during a semester.