Detail výsledku
Test Time Reduction by Scan Chain Reordering
In this paper, methodology for scan chain optimisation performed after physical layout is presented. It is shown how the methodology can be used to decrease test time of component under test if scan chain is reorganized. The principles of the methodology are based on eliminating some types of faults in the physical layout and subsequent reduction of the number of test vectors needed to test the scan chain. As a result, component test application time is decreased. The methodology was verified on several circuits, experimental results are provided and discussed. It is expected that the results of our methodology can be used in mass production of electronic components where any reduction of test time is of great importance.
scan chain, reorganization, reordering, physical layout, fault, diagnostics, test
@inproceedings{BUT91265,
author="Pavel {Bartoš}",
title="Test Time Reduction by Scan Chain Reordering",
booktitle="Proceedings of the 17th Conference STUDENT EEICT 2011",
year="2011",
series="Volume 3",
pages="564--568",
publisher="Faculty of Electrical Engineering and Communication BUT",
address="Brno",
isbn="978-80-214-4273-3"
}Matematické a inženýrské metody pro vývoj spolehlivých a bezpečných paralelních a distribuovaných počítačových systémů, GAČR, Doktorské granty, GD102/09/H042, zahájení: 2009-01-30, ukončení: 2012-12-31, ukončen
Výzkum informačních technologií z hlediska bezpečnosti, MŠMT, Institucionální prostředky SR ČR (např. VZ, VC), MSM0021630528, zahájení: 2007-01-01, ukončení: 2013-12-31, řešení
Zvyšování spolehlivost a provozuschopnosti v obvodech SoC, GAČR, Standardní projekty, GA102/09/1668, zahájení: 2009-01-01, ukončení: 2011-12-31, ukončen