Detail výsledku
Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference Accelerators
Mrázek Vojtěch, Ing., Ph.D., UPSY (FIT)
Sekanina Lukáš, prof. Ing., Ph.D., UPSY (FIT)
A new field programmable gate array (FPGA)-based emulation platform is proposed
to accelerate fault tolerance analysis of inference accelerators of convolutional
neural networks (CNN). For a given CNN model, hardware accelerator architecture,
and FT analysis target, an FPGA-based CNN implementation is generated (with the
help of the Tengine framework), and fault injection logic is added. In our first
case study, we report how the classification accuracy drop depends on the faults
injected into multipliers used in Multiply-and-Accumulate Units of NVDLA
inference accelerator executing ResNet-18 CNN. The FT analysis emulated on Zynq
UltraScale+ SoC is an order of magnitude faster than software emulation.
Fault injection, hardware accelerator, convolutional neural network inference
@inproceedings{BUT193424,
author="Filip {Masár} and Vojtěch {Mrázek} and Lukáš {Sekanina}",
title="Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference Accelerators",
booktitle="2025 Design, Automation & Test in Europe Conference & Exhibition (DATE)",
year="2025",
pages="1--2",
publisher="Institute of Electrical and Electronics Engineers",
address="Lyon",
doi="10.23919/DATE64628.2025.10992992",
isbn="978-3-9826741-0-0"
}