Nonstandard Automatic Test Pattern Generation Based on Neural Network Theory

The paper deals with an unusual application of the Hopfield neural network for test pattern generation of combinational logic circuits. The neural subnets generating signals satisfying the functions of some standard gates are derived and their merging to the net representing complex circuit is presented. To generate a test pattern, two identical nets are created, the fault is injected to the arbitrary net and both nets outputs are combined together to check them for inequality. The nets themselves look for their neuron outputs (signals of logical gates) satisfying all signal combinations and thus find the input signals detecting the fault being modelled. The method has been verified on examples of logical circuits containing tens of gates. The results are presented.