Publication Details

Optimizing SW/HW Architecture for Parallel Embedded Systems - A Case Study

DVOŘÁK, V. Optimizing SW/HW Architecture for Parallel Embedded Systems - A Case Study. Proceedings of the the International Workshop on Discrete-Event System Design, DESDes'01. Przytok near Zielona Gora, POLAND: Publishing House of Zielona Gora Technical University, 2001. p. 103-108. ISBN: 83-85911-62-6.

Type

conference paper

Language

English

Authors

Dvořák Václav, prof. Ing., DrSc.

Keywords

Parallel Embedded Systems, Multiprocessor Simulation, Hardware Description Language

Abstract

The paper addresses the issue of prototyping hw/sw architecture of application-specific multi-processor systems (recently on a chip). Performance prediction of these systems, either bus-based SMPs or message-passing networks of DSPs, is undertaken using a CSP-based tool Transim. Variations in processor count, clock rate, link speed, bus bandwidth, cache line, as well as in partitioning and mapping the resulting sw components to processors can be easily accounted for. The technique is demonstrated on parallel FFT on 2 to 8 processors.

Published

2001

Pages

103–108

Proceedings

Proceedings of the the International Workshop on Discrete-Event System Design, DESDes'01

ISBN

83-85911-62-6

Publisher

Publishing House of Zielona Gora Technical University

Place

Przytok near Zielona Gora, POLAND

BibTeX

@inproceedings{BUT5579,
  author="Václav {Dvořák}",
  title="Optimizing SW/HW Architecture for Parallel Embedded Systems - A Case Study",
  booktitle="Proceedings of the the International Workshop on Discrete-Event System Design, DESDes'01",
  year="2001",
  pages="103--108",
  publisher="Publishing House of Zielona Gora Technical University",
  address="Przytok near Zielona Gora, POLAND",
  isbn="83-85911-62-6"
}