Publication Details

Instructor Selector Generation from Architecture Description

TRMAČ, M.; HUSÁR, A.; HRANÁČ, J.; HRUŠKA, T.; MASAŘÍK, K. Instructor Selector Generation from Architecture Description. 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Masaryk University, 2010. p. 167-174. ISBN: 978-80-87342-10-7.
Czech title
Generování selektoru instrukcí z popisu architektury
Type
conference paper
Language
English
Authors
Trmač Miloslav, Mgr.
Husár Adam, Ing., Ph.D.
Hranáč Jan, Ing.
Hruška Tomáš, prof. Ing., CSc. (DIFS)
Masařík Karel, Ing., Ph.D. (CM-SDE)
Keywords

compiler, instruction selection, LLVM, ISAC

Abstract

We describe an automated way to generate data for a practical LLVM instruction selector based on machine-generated description of the target architecture at register transfer level. The generated instruction selector can handle arbitrarily complex machine instructions with no internal control flow, and can automatically find and take advantage of arithmetic properties of an instructions, specialized pseudo-registers and special cases of immediate operands.

Published
2010
Pages
167–174
Proceedings
6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science
ISBN
978-80-87342-10-7
Publisher
Masaryk University
Place
Brno
BibTeX 
@inproceedings{BUT37045,
  author="Miloslav {Trmač} and Adam {Husár} and Jan {Hranáč} and Tomáš {Hruška} and Karel {Masařík}",
  title="Instructor Selector Generation from Architecture Description",
  booktitle="6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
  year="2010",
  pages="167--174",
  publisher="Masaryk University",
  address="Brno",
  isbn="978-80-87342-10-7"
}
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