Publication Details

Hardware Accelerators for Cartesian Genetic Programming

VAŠÍČEK, Z.; SEKANINA, L. Hardware Accelerators for Cartesian Genetic Programming. Eleventh European Conference on Genetic Programming. Lecture Notes in Computer Science. Berlin: Springer Verlag, 2008. p. 230-241. ISBN: 978-3-540-78670-2.
Czech title
Obvodové akcelerátory pro kartézské genetické programování
Type
conference paper
Language
English
Authors
Vašíček Zdeněk, doc. Ing., Ph.D. (DCSY)
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
Keywords

cartesian genetic programming, field programmable gate array, evolutionary design

Abstract

A new class of FPGA-based accelerators is presented for Cartesian Genetic Programming (CGP).  The accelerators contain a genetic engine which is reused in all applications. Candidate programs (circuits) are evaluated using application-specific virtual reconfigurable circuit (VRC) and fitness unit. Two types of VRCs are proposed. The first one is devoted for symbolic regression problems over the fixed point representation. The second one is designed for evolution of logic circuits. In both cases a significant speedup of evolution (30-40 times) was obtained in comparison with a highly optimized software implementation of CGP. This speedup can be increased by creating multiple fitness units.

Published
2008
Pages
230–241
Proceedings
Eleventh European Conference on Genetic Programming
Series
Lecture Notes in Computer Science
Volume
4971
ISBN
978-3-540-78670-2
Publisher
Springer Verlag
Place
Berlin
BibTeX 
@inproceedings{BUT30754,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="Hardware Accelerators for Cartesian Genetic Programming",
  booktitle="Eleventh European Conference on Genetic Programming",
  year="2008",
  series="Lecture Notes in Computer Science",
  volume="4971",
  pages="230--241",
  publisher="Springer Verlag",
  address="Berlin",
  isbn="978-3-540-78670-2",
  url="https://www.fit.vut.cz/research/publication/8590/"
}
Back to top