Publication Details

Návrh a implementace jednotky pro analýzu paketů

MIKUŠEK, P. Návrh a implementace jednotky pro analýzu paketů. Proceedings of the 11th Conference and Competition STUDENT EEICT 2005. Brno: Vysoké učení technické v Brně, 2005. s. 145-148. ISBN: 80-214-2888-0.

English title

Design and Implementation of Processing Unit for Packet Analysis

Type

conference paper

Language

Czech

Authors

Mikušek Petr, Ing.

Keywords

RISC, FPGA, VHDL, COMBO6, packet analysis

Abstract

This paper presents architecture of Header Field Extractor processor, which is dedicated for packet analysis. It extracts specific control information from packet's headers, which are important for further packet processing. Processor is based on RISC architecture and it is controlled by instruction set dedicated for packet analysis. As a target technology the Field Programmable Gate Array (FPGA) is supposed.

Published

2005

Pages

145–148

Proceedings

Proceedings of the 11th Conference and Competition STUDENT EEICT 2005

Conference

STUDENT EEICT 2005, Brno, CZ

ISBN

80-214-2888-0

Publisher

Vysoké učení technické v Brně

Place

Brno

BibTeX

@inproceedings{BUT192636,
  author="Petr {Mikušek}",
  title="Návrh a implementace jednotky pro analýzu paketů",
  booktitle="Proceedings of the 11th Conference and Competition STUDENT EEICT 2005",
  year="2005",
  pages="145--148",
  publisher="Vysoké učení technické v Brně",
  address="Brno",
  isbn="80-214-2888-0"
}