Publication Details

RT Level Test Scheduling Procedure

HLAVIČKA, J.; KOTÁSEK, P.; KOTÁSEK, Z. RT Level Test Scheduling Procedure. Proceedings on Design Metodologies for Microelectronics. Smolenice: Slovak Academy of Science, 1995. p. 264-271.

Type

conference paper

Language

English

Authors

Hlavička Jan
Kotásek Petr, Ing.
Kotásek Zdeněk, doc. Ing., CSc.

Keywords

Design for Testability, built-in-self test, test scheduling, graph coloring

Annotation

It is shown how the problem of concurrent test application can be transformed to the one of Test Application Conflict Graph coloring and covering its nodes. Different conflicts, that appear during an RTL circuit test scheduling, can be taken into account. One of them, the test application time of different units, is discussed in details. It is also shown how the TACG concept can be utilized for a test scheduling of tests with unequal test length.

Published

1995

Pages

264–271

Proceedings

Proceedings on Design Metodologies for Microelectronics

Publisher

Slovak Academy of Science

Place

Smolenice

BibTeX

@inproceedings{BUT191922,
  author="Jan {Hlavička} and Petr {Kotásek} and Zdeněk {Kotásek}",
  title="RT Level Test Scheduling Procedure",
  booktitle="Proceedings on Design Metodologies for Microelectronics",
  year="1995",
  pages="264--271",
  publisher="Slovak Academy of Science",
  address="Smolenice"
}