Testability Analysis Based on Discrete Mathematics Concepts

design-for-testability, testability analysis, i paths, scan

Most of testability methodologies published so far are based on the circuit structure analysis and heuristic approaches. One of the possibilities is to analyze the VHDL description of the circuit. In our opinion, the implementation of a testability analysis methodology requires to extract the structure of the circuit from the internal representation of the circuit and its transformation into a useable database first. The testability analysis algorithms then operate on the database rather than on the data representing the internal structure of the circuit. In our research activities we deal with the Register Transfer Level testability analysis. Our methodology is based on evaluating the possible role of registers during the test application on the basis of which the elements are included into sets, the structure of the circuit and the transparency properties of elements are taken into account during the analysis. Once the sets are created, different relations between elements can be investigated. Such approach allows to identify different configurations of the circuit and to describe their properties by means of the discrete mathematic concepts and tools.