Publication Details

RT Level Testability Analysis In PROLOG Enviroment

KOTÁSEK, Z.; ZBOŘIL, F. RT Level Testability Analysis In PROLOG Enviroment. Proceedings of the DDECS'97. Ostrava: 1997. p. 47-52. ISBN: 80-85988-19-4.

Czech title

Type

conference paper

Language

English

Authors

Kotásek Zdeněk, doc. Ing., CSc.
Zbořil František, doc. Ing., CSc. (DITS)

Keywords

RT Level Testability Analysis, RTL Circuit Transformation, PROLOG

Abstract

The paper deals with the principles of the RT level testability analysis. The prescription for an RTL circuit transformation to a labelled directed graph and its representation in PROLOG environment are presented. The methodology for the RT level testability analysis and the principles of its implementation are described in detail.

Published

1997

Pages

47–52

Proceedings

Proceedings of the DDECS'97

ISBN

80-85988-19-4

Place

Ostrava

BibTeX

@inproceedings{BUT191448,
  author="Zdeněk {Kotásek} and František {Zbořil}",
  title="RT Level Testability Analysis In  PROLOG Enviroment",
  booktitle="Proceedings of the  DDECS'97",
  year="1997",
  pages="47--52",
  address="Ostrava",
  isbn="80-85988-19-4"
}