Technology Mapping for PAIG Optimized Polymorphic Circuits

polymorphic electronics, polymorphic gates, PAIG synthesis, PAIG technology mapping

The concept of polymorphic electronics allows to efficiently implement two or more functions in a single circuit, whereas the currently selected function depends on the state of the circuit operating environment. The key components of such circuits are polymorphic gates. Since the introduction of polymorphic electronics, few tens of polymorphic gates have been published. However, a large number of them exhibit parameters that fall behind ubiquitous CMOS technology. As a result of that, the perspective of their utilization for real applications becomes rather bleak. In recent years, several complete libraries of CMOS-compatible polymorphic gates were proposed. Synthesis of polymorphic circuits achieves a higher degree of complexity in comparison to the synthesis of an ordinary digital circuit. In past, many of yet proposed polymorphic circuits have been synthesized using evolutionary principles (EA, CGP, etc.). Research done in recent years indicates that the problem of scalable synthesis technique for the synthesis of complex polymorphic circuits could be solved by multi-level synthesis techniques such as And-Inverter-Graphs. The PAIG (Polymorphic And-Inverter-Graphs) concept and synthesis techniques based on it seems to be viable approach. This paper shows a how modern polymorphic gates could be used to obtain effective implementation of a real polymorphic circuit, synthesized by a PAIG based tool.