Publication Details

Design of the Special Fast Reconfigurable Chip Using Common FPGA

SEKANINA, L.; RŮŽIČKA, R. Design of the Special Fast Reconfigurable Chip Using Common FPGA. Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000. Smolenice: unknown, 2000. p. 161-168. ISBN: 80-968320-3-4.
Czech title
Návrh speciálního rychle rekonfigurovatelného obvodu s využitím běžného FPGA
Type
conference paper
Language
English
Authors
Sekanina Lukáš, prof. Ing., Ph.D. (DCSY)
Růžička Richard, doc. Ing., Ph.D., MBA (DCSY)
URL
Keywords

reconfigurable circuits, evolvable hardware

Abstract

Some applications require chips with fast partial reconfiguration. These requirements are traditionally satisfied by a special chip design, but it is usually a very expensive solution. This paper describes a new approach. Special fast partially reconfigurable chip is implemented with a common FPGA. The format of the configuration bit stream is suggested and optimized according to the given task. Result chip offers many good properties, but some problems with scalability can appear.

Annotation
Published
2000
Pages
161–168
Proceedings
Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000
ISBN
80-968320-3-4
Publisher
unknown
Place
Smolenice
BibTeX 
@inproceedings{BUT17637,
  author="Lukáš {Sekanina} and Richard {Růžička}",
  title="Design of the Special Fast Reconfigurable Chip Using Common FPGA",
  booktitle="Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000",
  year="2000",
  pages="161--168",
  publisher="unknown",
  address="Smolenice",
  isbn="80-968320-3-4",
  url="http://www.fit.vutbr.cz/~sekanina/publ/ddecs00/rechip.pdf"
}
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