Publication Details

Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis

VAŠÍČEK Zdeněk, MRÁZEK Vojtěch and SEKANINA Lukáš. Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis. In: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE). Valencia: Institute of Electrical and Electronics Engineers, 2024, pp. 1-6. ISBN 979-8-3503-4859-0.
Czech title
Automatizovaný návrh přibližně počítajících obvodů řízený verifikovatelností
Type
conference paper
Language
english
Authors
Keywords

approximate computing, approximate arithmetic circuit, formal analysis, constrained verification

Abstract

A fundamental assumption for search-based circuit approximation methods is the ability to massively and efficiently traverse the search space and evaluate candidate solutions. For complex approximate circuits (adders and multipliers), common error metrics, and error analysis approaches (SAT solving, BDD analysis), we perform a detailed analysis to understand the behavior of the error analysis methods under constrained resources, such as limited execution time. In addition, we show that when evaluating the error of a candidate approximate circuit, it is highly beneficial to reuse knowledge obtained during the evaluation of previous circuit instances to reduce the total design time. When an adaptive search strategy that drives the search towards promptly verifiable approximate circuits is employed, the method can discover circuits that exhibit better trade-offs between error and desired parameters (such as area) than the same method with unconstrained verification resources and within the same overall time budget. For 16-bit and 20-bit approximate multipliers, it was possible to achieve a 75% reduction in area when compared with the baseline method.

Published
2024
Pages
1-6
Proceedings
2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Conference
Design, Automation and Test in Europe, Valencia, ES
ISBN
979-8-3503-4859-0
Publisher
Institute of Electrical and Electronics Engineers
Place
Valencia, ES
EID Scopus
BibTeX
@INPROCEEDINGS{FITPUB13136,
   author = "Zden\v{e}k Va\v{s}\'{i}\v{c}ek and Vojt\v{e}ch Mr\'{a}zek and Luk\'{a}\v{s} Sekanina",
   title = "Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis",
   pages = "1--6",
   booktitle = "2024 Design, Automation \& Test in Europe Conference \& Exhibition (DATE)",
   year = 2024,
   location = "Valencia, ES",
   publisher = "Institute of Electrical and Electronics Engineers",
   ISBN = "979-8-3503-4859-0",
   language = "english",
   url = "https://www.fit.vut.cz/research/publication/13136"
}
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