Detail výsledku

An Evolvable Combinational Unit for FPGAs

SEKANINA, L.; FRIEDL, Š. An Evolvable Combinational Unit for FPGAs. COMPUTING AND INFORMATICS, 2004, vol. 23, no. 5, p. 461-486. ISSN: 1335-9150.
Typ
článek v časopise
Jazyk
angličtina
Autoři
Sekanina Lukáš, prof. Ing., Ph.D., UPSY (FIT)
Friedl Štěpán, Ing.
Abstrakt

A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evolutionary algorithm was described in VHDL independently of a target platform, i.e. as a soft IP core, and realized in the COMBO6 card. In many cases the unit is able to evolve (i.e. to design) the required function automatically and autonomously, in a few seconds, only on the basis of interactions with an environment. A number of circuits were successfully evolved directly in the FPGA, in particular, 3-bit multipliers, adders, multiplexers and parity encoders. The evolvable unit was also tested in a simulated dynamic environment and used to design various circuits specified by randomly generated truth tables.

Klíčová slova

combinational circuit, evolutionary design, evolvable hardware, field programmable gate array

URL
Rok
2004
Strany
461–486
Časopis
COMPUTING AND INFORMATICS, roč. 23, č. 5, ISSN 1335-9150
BibTeX 
@article{BUT46258,
  author="Lukáš {Sekanina} and Štěpán {Friedl}",
  title="An Evolvable Combinational Unit for FPGAs",
  journal="COMPUTING AND INFORMATICS",
  year="2004",
  volume="23",
  number="5",
  pages="461--486",
  issn="1335-9150",
  url="http://www.fit.vutbr.cz/~sekanina/publ/cai/cai04.pdf"
}
Projekty
Metody návrhu aplikací založených na vyvíjejících se obvodech, GAČR, Postdoktorandské granty, GP102/03/P004, zahájení: 2003-01-01, ukončení: 2005-12-31, ukončen
Moderní metody syntézy číslicových systémů, GAČR, Standardní projekty, GA102/04/0737, zahájení: 2004-01-01, ukončení: 2006-12-31, ukončen
Výzkumné skupiny
EvoAI Hardware (VZ EHW)
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru