Detail výsledku

Efficient Image Filtering and Information Reduction in Reconfigurable Logic

TORRESEN, J.; BAKKE, J.; SEKANINA, L. Efficient Image Filtering and Information Reduction in Reconfigurable Logic. Proc. of 2004 Norchip conference. Oslo: IEEE Computer Society Press, 2004. p. 63-66. ISBN: 0-7803-8510-1.
Typ
článek ve sborníku konference
Jazyk
angličtina
Autoři
Torresen Jim, prof. Dr. Ing.
Bakke Jorgen
Sekanina Lukáš, prof. Ing., Ph.D., UPSY (FIT)
Abstrakt

An automatic sign detection system could be important in enhancing traffic safety. Such a system would have to be able to provide high speed processing in its real-time environment. In this paper, we show how one of the time consuming parts of a speed limit detection algorithm can be implemented in reconfigurable logic to speed up the processing. Results indicate that the present system would be able to handle 12 images per second. IEEE Catalog Number: 04EX861

Klíčová slova

evolvable hardware, image processing, traffic sign

URL
Rok
2004
Strany
63–66
Sborník
Proc. of 2004 Norchip conference
Konference
Norchip conference 2004
ISBN
0-7803-8510-1
Vydavatel
IEEE Computer Society Press
Místo
Oslo
BibTeX 
@inproceedings{BUT17579,
  author="Jim {Torresen} and Jorgen {Bakke} and Lukáš {Sekanina}",
  title="Efficient Image Filtering and Information Reduction in Reconfigurable Logic",
  booktitle="Proc. of 2004 Norchip conference",
  year="2004",
  pages="63--66",
  publisher="IEEE Computer Society Press",
  address="Oslo",
  isbn="0-7803-8510-1",
  url="http://heim.ifi.uio.no/~jimtoer/Torresen_Norchip04.pdf"
}
Projekty
Metody návrhu aplikací založených na vyvíjejících se obvodech, GAČR, Postdoktorandské granty, GP102/03/P004, zahájení: 2003-01-01, ukončení: 2005-12-31, ukončen
Výzkumné skupiny
EvoAI Hardware (VZ EHW)
Pracoviště
Ústav počítačových systémů (UPSY)
Nahoru