Multicore design in FPGA of ZYNQ for demonstration of RPMsg Lite protocol

The design contains two MicroBlaze processors within one FPGA of ZYNQ. Both processors execute program from their own local memory, which is situated in block RAM memory (BRAM) within the FPGA part. The processors also use the common memory which is also situated in block RAM memory within FPGA part. This layout enables to demonstrate functionality of RPMsg Lite protocol. RPMsg protocol enables two heterogeneous processor cores to communicate using a shared memory. The technique uses single-writer-single-reader circular buffers to pass message buffers to the other core. This approach does not require any multicore synchronization element. The RPMsg Lite protocol is meant to be a solution for Mixed critical systems applications because of its feature to split and instantiate the system into independent blocks or subsystems. The design uses a wide FPGA flexibility of XC7Z020-1CLG484C device. All FPGA designs were synthesized in Xilinx Vivado 2016.3.