Detail publikace

An Evolvable Hardware System in Xilinx Virtex II Pro FPGA

VAŠÍČEK, Z.; SEKANINA, L. An Evolvable Hardware System in Xilinx Virtex II Pro FPGA. International Journal of Innovative Computing and Applications, 2007, vol. 1, no. 1, p. 63-73. ISSN: 1751-648X.
Název česky
An Evolvable Hardware System in Xilinx Virtex II Pro FPGA
Typ
článek v časopise
Jazyk
anglicky
Autoři
Vašíček Zdeněk, doc. Ing., Ph.D. (UPSY)
Sekanina Lukáš, prof. Ing., Ph.D. (UPSY)
URL
Klíčová slova

image filter, evolvable hardware, FPGA

Abstrakt

In this paper, a new circuit architecture for image filter evolution is proposed. The evolvable system is based on the implementation of a search algorithm in the PowerPC processor which is available in Xilinx Virtex II Pro FPGAs. Candidate filters are evaluated in a domain-specific virtual reconfigurable circuit implemented using a reconfigurable logic of the same FPGA. As the PowerPC processor enables to execute more sophisticated search algorithms than an original solely circuit-based solution, a higher performance can be obtained. In the FPGA, a resulting human-competitive filter can be evolved in 15 seconds in average.  

Rok
2007
Strany
63–73
Časopis
International Journal of Innovative Computing and Applications, roč. 1, č. 1, ISSN 1751-648X
BibTeX 
@article{BUT45160,
  author="Zdeněk {Vašíček} and Lukáš {Sekanina}",
  title="An Evolvable Hardware System in Xilinx Virtex II Pro FPGA",
  journal="International Journal of Innovative Computing and Applications",
  year="2007",
  volume="1",
  number="1",
  pages="63--73",
  issn="1751-648X"
}
Nahoru