Detail publikace

High Availability Fault Tolerant Architectures Implemented into FPGAs

STRAKA, M.; KOTÁSEK, Z. High Availability Fault Tolerant Architectures Implemented into FPGAs. 12th EUROMICRO Conference on Digital System Design DSD 2009. Patras: IEEE Computer Society, 2009. p. 108-116. ISBN: 978-0-7695-3782-5.
Název česky
High Availability Fault Tolerant Architectures Implemented into FPGAs
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Straka Martin, Ing., Ph.D.
Kotásek Zdeněk, doc. Ing., CSc.
Klíčová slova

TMR, availability, Markov reliability model, FPGA, fault tolerant systems, checker

Abstrakt

In the paper, the methodology of fault tolerant systems design based on FPGA are presented. The architectures are based both on duplex and TMR systems to which fault detection capabilities are added, the use of on-line checkers for this purpose is demonstrated. It is described how reliability and availability parameters in TMR and duplex structures with checkers can be increased. To demonstrate this, analytical calculations based on Markov reliability model are used. It is also shown how the availability parameters can be affected by the operating environment into which the fault tolerant system is implemented. The principles of generating sequence of FT architectures with different level of diagnostic are presented.

Rok
2009
Strany
108–116
Sborník
12th EUROMICRO Conference on Digital System Design DSD 2009
ISBN
978-0-7695-3782-5
Vydavatel
IEEE Computer Society
Místo
Patras
BibTeX 
@inproceedings{BUT30207,
  author="Martin {Straka} and Zdeněk {Kotásek}",
  title="High Availability Fault Tolerant Architectures Implemented into FPGAs",
  booktitle="12th EUROMICRO Conference on Digital System Design DSD 2009",
  year="2009",
  pages="108--116",
  publisher="IEEE Computer Society",
  address="Patras",
  isbn="978-0-7695-3782-5"
}
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