Detail publikace

Reducing the Number of Transistors in Digital Circuits Using Gate-Level Evolutionary Design

GAJDA, Z.; SEKANINA, L. Reducing the Number of Transistors in Digital Circuits Using Gate-Level Evolutionary Design. 2007 Genetic and Evolutionary Computation Conference. New York: Association for Computing Machinery, 2007. p. 245-252. ISBN: 9781595936974.
Název česky
Reducing the Number of Transistors in Digital Circuits Using Gate-Level Evolutionary Design
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Gajda Zbyšek, Ing., Ph.D. (VZ EHW)
Sekanina Lukáš, prof. Ing., Ph.D. (UPSY)
URL
Klíčová slova

digital circuit, evolutionary design, cartesian genetic programming

Abstrakt

This paper shows that the evolutionary design of digital circuits which is
conducted at the gate level is able to produce human-competitive circuits at the
transistor level. In addition to standard gates, we utilize unconventional gates
(such as the NAND/NOR gate and NOR/NAND gate) that consist of a few transistors
but exhibit non-trivial 3-input logic functions. Novel implementations of adders
and majority circuits evolved using these gates contain fewer transistors than
the smallest existing implementations of these circuits. Moreover, it was shown
that the use of these gates significantly improves the success rate of the search
process.

Rok
2007
Strany
245–252
Sborník
2007 Genetic and Evolutionary Computation Conference
Konference
Genetic and Evolutionary Computation Conference , London, GB
ISBN
9781595936974
Vydavatel
Association for Computing Machinery
Místo
New York
BibTeX 
@inproceedings{BUT28799,
  author="Zbyšek {Gajda} and Lukáš {Sekanina}",
  title="Reducing the Number of Transistors in Digital Circuits Using Gate-Level Evolutionary Design",
  booktitle="2007 Genetic and Evolutionary Computation Conference",
  year="2007",
  pages="245--252",
  publisher="Association for Computing Machinery",
  address="New York",
  isbn="9781595936974",
  url="http://www.fit.vutbr.cz/~sekanina/publ/gecco07/gajda-sekanina.pdf"
}
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