Detail publikace

Checker Design for On-line Testing of Xilinx FPGA Communication

STRAKA, M.; TOBOLA, J.; KOTÁSEK, Z. Checker Design for On-line Testing of Xilinx FPGA Communication. In The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. Rome: IEEE Computer Society, 2007. p. 152-160. ISBN: 0-7695-2885-6.
Název česky
Checker Design for On-line Testing of Xilinx FPGA Communication
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Straka Martin, Ing., Ph.D.
Tobola Jiří, Ing., MBA (PR FIT)
Kotásek Zdeněk, doc. Ing., CSc.
Klíčová slova

Communication Protocol Testing, Fault Tolerant Systems, checker design

Abstrakt

In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemented in Xilinx FPGA based designs. A formal language enabling to describe the protocol was created for this purpose together with a generator of the formal description into VHDL code. The VHDL code can be then used for the synthesis of the checker structure and used in applications with Xilinx FPGAs.

Rok
2007
Strany
152–160
Sborník
The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISBN
0-7695-2885-6
Vydavatel
IEEE Computer Society
Místo
Rome
BibTeX 
@inproceedings{BUT28609,
  author="Martin {Straka} and Jiří {Tobola} and Zdeněk {Kotásek}",
  title="Checker Design for On-line Testing of Xilinx FPGA Communication",
  booktitle="The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems",
  year="2007",
  pages="152--160",
  publisher="IEEE Computer Society",
  address="Rome",
  isbn="0-7695-2885-6"
}
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