Detail publikace

Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates

SEKANINA, L. Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates. In 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Gliwice: IEEE Computer Society, 2007. p. 243-246. ISBN: 1424411610.
Název česky
Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Sekanina Lukáš, prof. Ing., Ph.D. (UPSY)
URL
Klíčová slova

digital circuit, polymorphic gate, adder, testing

Abstrakt

TBD

Rok
2007
Strany
243–246
Sborník
2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
ISBN
1424411610
Vydavatel
IEEE Computer Society
Místo
Gliwice
BibTeX 
@inproceedings{BUT28586,
  author="Lukáš {Sekanina}",
  title="Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates",
  booktitle="2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems",
  year="2007",
  pages="243--246",
  publisher="IEEE Computer Society",
  address="Gliwice",
  isbn="1424411610"
}
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