Detail publikace

Towards Formal Relaxed Equivalence Checking in Approximate Computing Methodology

HOLÍK, L.; LENGÁL, O.; ROGALEWICZ, A.; SEKANINA, L.; VAŠÍČEK, Z.; VOJNAR, T. Towards Formal Relaxed Equivalence Checking in Approximate Computing Methodology. 2nd Workshop on Approximate Computing (WAPCO 2016). Prague: 2016. p. 1-6.
Typ
článek ve sborníku konference
Jazyk
anglicky
Autoři
Holík Lukáš, doc. Mgr., Ph.D. (UITS)
Lengál Ondřej, Ing., Ph.D. (UITS)
Rogalewicz Adam, doc. Mgr., Ph.D. (UITS)
Sekanina Lukáš, prof. Ing., Ph.D. (UPSY)
Vašíček Zdeněk, doc. Ing., Ph.D. (UPSY)
Vojnar Tomáš, prof. Ing., Ph.D. (UITS)
URL
Abstrakt

Most design automation methods developed for approximate computing evaluate candidate solutions by applying a set of input vectors and measuring the error of the output vectors with respect to an exact solution. This approach is not, however, applicable when approximating complex combinational or sequential circuits since the error is not computed precisely enough. This paper surveys various methods of formal verification that could be extended for purposes of determining the error of approximation more precisely and formulates this task through a notion of formal relaxed equivalence checking.

Rok
2016
Strany
1–6
Sborník
2nd Workshop on Approximate Computing (WAPCO 2016)
Konference
HiPEAC 2016, Praha, CZ
Místo
Prague
BibTeX 
@inproceedings{BUT168446,
  author="Lukáš {Holík} and Ondřej {Lengál} and Adam {Rogalewicz} and Lukáš {Sekanina} and Zdeněk {Vašíček} and Tomáš {Vojnar}",
  title="Towards Formal Relaxed Equivalence Checking in Approximate Computing Methodology",
  booktitle="2nd Workshop on Approximate Computing (WAPCO 2016)",
  year="2016",
  pages="1--6",
  address="Prague",
  url="http://wapco.inf.uth.gr/index.html"
}
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