Product Details

Nástroje pro generování odolných architektur a hlídacích obvodů z jazyka VHDL

Created: 2015

English title
Tools enabling to develop fault tolerant architectures and checkers from VHDL
Type
software
License
Use of the result by another entity is possible without acquiring a license in some cases
License Fee
The licensor does not require a license fee for the result
Authors
Straka Martin, Ing., Ph.D.
Keywords

tool, vhdl, fault tolerant architecture, checker

Description

Tools for generating different types of fault tolerant architectures from VHDL description of the components and their checkers.

Location

http://www.fit.vutbr.cz/research/grants/index.php.cs?id=618

Projects
Methodologies for Fault Tolerant Systems Design Development, Implementation and Verification, MŠMT, COST CZ (2011-2017), LD12036, 2012-2015, completed
Research groups
Dependable Digital Systems Research Group (RG DEPSYS)
Departments
Department of Computer Systems (DCSY)
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