Publication Details

Web-Based Simulator of Superscalar RISC-V Processors

JAROŠ, J.; MAJER, M.; HORKÝ, J.; VÁVRA, J. Web-Based Simulator of Superscalar RISC-V Processors. Atlanta, GA: 2024. p. 1-2.
Czech title
Webový simulátor superskalárních procesorů RISC-V
Type
presentation, poster
Language
English
Authors
Jaroš Jiří, doc. Ing., Ph.D. (DCSY)
Majer Michal, Ing.
Horký Jakub, Ing.
Vávra Jan, Ing.
URL
Keywords

Web-based simulator, RISC-V processor, superscalar processor 

Abstract

Mastering computational architectures is essential for developing fast and
power-efficient programs. Our advanced simulator empowers both IT students and
professionals to grasp the fundamentals of superscalar processors and HW-SW
co-design. With customizable processor architecture, full C compiler support, and
detailed performance statistics, this tool offers a comprehensive learning
experience. Enjoy the convenience of a modern, web-based GUI to enhance your
understanding and skills.

Published
2024
Pages
1–2
Conference
The International Conference for High Performance Computing, Networking, Storage, and Analysis, Georgia World Congress Center, Atlanta,Georgia, US
Place
Atlanta, GA
BibTeX 
@misc{BUT196523,
  author="Jiří {Jaroš} and Michal {Majer} and Jakub {Horký} and Jan {Vávra}",
  title="Web-Based Simulator of Superscalar RISC-V Processors",
  year="2024",
  pages="1--2",
  address="Atlanta, GA",
  url="https://sc24.supercomputing.org/proceedings/poster/poster_files/post150s2-file3.pdf",
  note="presentation, poster"
}
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